REV. 5.0.3 2.90V TO 5.5V UART WITH 32-BYTE FIFO PIN DESCRIPTIONS NAME 44- PLCC
參數(shù)資料
型號(hào)： ST16C650AIJ44-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 23/50頁(yè)
文件大小： 0K
描述： IC UART FIFO 32B 44PLCC
標(biāo)準(zhǔn)包裝： 27
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 32 字節(jié)
規(guī)程： 打印機(jī)，RS232，RS422，RS485
電源電壓： 2.9 V ~ 5.5 V
帶并行端口： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
ST16C650A
3
REV. 5.0.3
2.90V TO 5.5V UART WITH 32-BYTE FIFO
PIN DESCRIPTIONS
NAME
44-
PLCC
PIN #
48-
TQFP
PIN #
TYPE
DESCRIPTION
16 (Intel) MODE DATA BUS INTERFACE. The SEL pin is connected to VCC.
A2
A1
A0
29
30
31
26
27
28
I
Address bus lines [2:0]
A2:A0 selects internal UART’s configuration registers.
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
4
3
2
47
46
45
44
43
IO
Data bus lines [7:0] (bidirectional)
IOR#
24
19
I
Input/Output Read (active low)
The falling edge instigates an internal read cycle and retrieves the data byte from
an internal register pointed by the address lines [A2:A0], places it on the data bus
to allow the host processor to read it on the leading edge. Its function is the same
as IOR, except it is active low. Either an active IOR# or IOR is required to transfer
data from 650A to CPU during a read operation. If this input is unused, it should
be connected to VCC to minimize supply current.
IOR
25
20
I
Input/Output Read (active high)
Same as IOR# but active high. If this input is unused, it should be connected to
GND to minimize supply current.
IOW#
20
16
I
Input/Output Write (active low)
The falling edge instigates the internal write cycle and the trailing edge transfers
the data byte on the data bus to an internal register pointed by the address lines
[A2:A0]. Its function is the same as IOW, except it is active low. Either an active
IOW# or IOW is required to transfer data from 650A to the Intel type CPU during a
write operation. If this input is unused, it should be connected to VCC to minimize
supply current.
IOW
21
17
I
Input/Output Write (active high)
Same as IOW# but active high. If this input is unused, it should be connected to
GND to minimize supply current.
CS0
14
9
I
Chip Select 0 input (active high)
This input selects the ST16C650A device. If CS1 or CS2# is used as the chip
select then this pin must be connected to VCC. The 650A is selected when all
three chip selects are active. See
CS1
15
10
I
Chip Select 1 input (active high)
This input selects the ST16C650A device. If CS0 or CS2# is used as the chip
select then this pin must be connected to VCC. The 650A is selected when all
three chip selects are active. See
CS2#
16
11
I
Chip Select 2 input (active low)
This input selects the ST16C650A device. If CS0 or CS1 is used as the chip select
then this pin must be connected to GND. The 650A is selected when all three chip
selects are active. See
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