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參數(shù)資料
| 型號： | ST16C580IQ48 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER |
| 中文描述： | 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 20/41頁 |
| 文件大?。?/td> | 244K |
| 代理商： | ST16C580IQ48 |
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ST16C580
20
Rev. 1.20
(FIFO’s enabled, FCR bit-0 = logic 1, FCR bit-3 = logic
0) and when there are no characters in the transmit
FIFO or transmit holding register, the -TXRDY pin will
be a logic 0. Once active the -TXRDY pin will go to a
logic 1 after the first character is loaded into the
transmit holding register.
Receive operation in mode “0”:
When the 580 is in mode “0” (FCR bit-0 = logic 0) or
in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 =
logic 0) and there is at least one character in the
receive FIFO, the -RXRDY pin will be a logic 0. Once
active the -RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
Transmit operation in mode “1”:
When the 580 is in FIFO mode ( FCR bit-0 = logic 1,
FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a
logic 0 if one or more FIFO locations are empty.
Receive operation in mode “1”:
When the 580 is in FIFO mode (FCR bit-0 = logic 1,
FCR bit-3 = logic 1) and the trigger level has been
reached, or a Receive Time Out has occurred, the -
RXRDY pin will go to a logic 0. Once activated, it will
go to a logic 1 after there are no more characters in the
FIFO.
FCR BIT 4-5: (logic 0 or cleared is the default condi-
tion, TX trigger level = 1)
These bits are used to set the trigger level for the
transmit FIFO interrupt. The ST16C580 will issue a
transmit empty interrupt when the number of charac-
ters in FIFO drops below the selected trigger level.
BIT-5
BIT-4
TX FIFO trigger level
0
0
1
1
0
1
0
1
1
4
8
14
FCR BIT 6-7: (logic 0 or cleared is the default condi-
tion, RX trigger level =8)
These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of charac-
ters in the FIFO equals the programmed trigger level.
However the FIFO will continue to be loaded until it is
full.
BIT-7
BIT-6
RX FIFO trigger level
0
0
1
1
0
1
0
1
1
4
8
14
Interrupt Status Register (ISR)
The 580 provides six levels of prioritized interrupts to
minimize external software interaction. The Interrupt
Status Register (ISR) provides the user with six inter-
rupt status bits. Performing a read cycle on the ISR will
provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowl-
edged until the pending interrupt is serviced. When-
ever the interrupt status register is read, the interrupt
status is cleared. However it should be noted that only
the current pending interrupt is cleared by the read. A
lower level interrupt may be seen after rereading the
interrupt status bits. The Interrupt Source Table 6
(below) shows the data values (bit 0-5) for the six
prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels:
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| ST16C580CJ44 | UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER |
| ST16C654CJ68 | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| ST16C654CQ100 | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| ST16C654 | Linear Voltage Regulator IC; Output Current Max:350mA; Supply Voltage Max:6V; Package/Case:8-TSSOP; Output Current:600mA; Output Voltage:5V; Current Rating:30.05A; Leaded Process Compatible:No; Output Voltage Max:5V |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ST16C580IQ48-F | 功能描述:UART 接口集成電路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C650 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| ST16C650A | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| ST16C650A_0508 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| ST16C650A_09 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
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