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參數(shù)資料
| 型號： | ST16C580IJ44 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER |
| 中文描述： | 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 22/41頁 |
| 文件大?。?/td> | 244K |
| 代理商： | ST16C580IJ44 |
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ST16C580
22
Rev. 1.20
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted data. The
receiver must be programmed to check the same
format. (normal default condition)
Logic 1 = EVEN Parity
is generated by forcing an even
the number of logic 1’s in the transmitted. The receiver
must be programmed to check the same format.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
LCR BIT-5 = logic 0, parity is not forced (normal
default condition)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive
data.
LCR
Bit-5
LCR
Bit-4
LCR
Bit-3
Parity selection
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
No parity
Odd parity
Even parity
Force parity “1”
Forced parity “0”
LCR BIT-6:
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
LCR BIT-7:
The internal baud rate counter latch and Enhance
Feature mode enable.
Logic 0 = Divisor latch disabled. (normal default
condition)
Logic 1 = Divisor latch and enhanced feature register
enabled.
Modem Control Register (MCR)
This register controls the interface with the modem or
a peripheral device.
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
MCR BIT-1:
Logic 0 = Force -RTS output to a logic 1. (normal
default condition)
Logic 1 = Force -RTS output to a logic 0.
Automatic RTS may be used for hardware flow control
by enabling EFR bit-6 (See EFR bit-6).
MCR BIT-2:
Logic 0 = Set -OP1 output to a logic 1. (normal default
condition)
Logic 1 = Set -OP1 output to a logic 0.
MCR BIT-3:
Logic 0 = Set -OP2 output to a logic 1. (normal default
condition)
Logic 1 = Set -OP2 output to a logic 0.
MCR BIT-4:
Logic 0 = Disable loop-back mode. (normal default
condition)
Logic 1 = Enable local loop-back mode (diagnostics).
MCR BIT-5:
Not used.
MCR BIT-6:
Logic 0 = Enable Modem receive and transmit input/
output interface. (normal default condition)
Logic 1 = Enable infrared IrDA receive and transmit
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C580IP40 | 制造商:EXAR 制造商全稱:EXAR 功能描述:UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER |
| ST16C580IQ48 | 制造商:EXAR 制造商全稱:EXAR 功能描述:UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER |
| ST16C580IQ48-F | 功能描述:UART 接口集成電路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C650 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| ST16C650A | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.90V TO 5.5V UART WITH 32-BYTE FIFO |
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