參數(shù)資料
型號(hào)： ST16C554D
廠商： Exar Corporation
英文描述： Quad UART with 16-Byte FIFO(四通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出）)
中文描述： 四路的UART具有16字節(jié)FIFO（四通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出））
文件頁(yè)數(shù)： 8/40頁(yè)
文件大小： 506K
代理商： ST16C554D
ST16C554/554D/68C554
8
Rev. 3.10
SYMBOL DESCRIPTION
Symbol
Pin
Signal
type
Pin Description
68
64
-RESET
RESET
37
27
I
Reset. - In the 16 mode a logic 1 on this pin will reset the
internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset
time. (See ST16C554D External Reset Conditions for ini-
tialization details.) When 16/-68 is a logic 0 (68 mode), this
pin functions similarly but, as an inverted reset interface
signal, -RESET.
-R/W
18
-
I
Read/Write Strobe (active low) - This function is associated
with the 68 mode only. This pin provides the combined
functions for Read or Write strobes. A logic 1 to 0 transition
transfers the contents of the CPU data bus (D0-D7) to the
register selected by -CS and A0-A4. Similarly a logic 0 to 1
transition places the contents of a 554D register selected by
-CS and A0-A4 on the data bus, D0-D7, for transfer to an
external CPU.
-RXRDY
38
-
O
Receive Ready (active low) - This function is associated
with 68 pin packages only. -RXRDY contains the wire OR-
ed status of all four receive channel FIFOs, RXRDY A-D.
A logic 0 indicates receive data ready status, i.e. the RHR
is full or the FIFO has one or more RX characters available
for unloading. This pin goes to a logic 1 when the FIFO/RHR
is full or when there are no more characters available in
either the FIFO or RHR. For 64/68 pin packages, individual
channel RX status is read by examining individual internal
registers via -CS and A0-A4 pin functions.
-TXRDY
39
-
O
Transmit Ready (active low) - This function is associated
with 68 pin package only. -TXRDY contains the wire OR-
ed status of all four transmit channel FIFOs, TXRDY A-D.
A logic 0 indicates a buffer ready status, i.e., at least one
location is empty and available in one of the TX channels (A-
D). This pin goes to a logic 1 when all four channels have no
more empty locations in the TX FIFO or THR.
VCC
VCC
13
4,21
35,52
47,64
I
Power supply inputs.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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