參數(shù)資料
型號(hào)： ST16C2450IQ48
廠商： EXAR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 2.97V TO 5.5V DUART
中文描述： 2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁(yè)數(shù)： 16/29頁(yè)
文件大?。?/td> 315K
代理商： ST16C2450IQ48
ST16C2450
2.97V TO 5.5V DUART
á
REV. 4.0.0
16
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
Table 7
for parity selection summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
LCR[5] = logic 0, parity is not forced (default).
LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
BIT-2
W
ORD
LENGTH
S
TOP
BIT
LENGTH
(B
IT
TIME
(
S
))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
T
ABLE
7: P
ARITY
SELECTION
LCR B
IT
-5 LCR B
IT
-4 LCR B
IT
-3
P
ARITY
SELECTION
X
X
0
No parity
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
Force parity to mark, “1”
1
1
1
Forced parity to space, “0”
相關(guān)PDF資料
PDF描述
ST16C2451 2.97V TO 5.5V DUART
ST16C2552CJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552IJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST162552 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552CJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST16C2450IQ48-F 功能描述:UART 接口集成電路 DUAL UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
ST16C2450IQ48TR-F 制造商:Exar Corporation 功能描述:UART 2-CH 1Byte FIFO 3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:ST16C2450IQ48TR-F
ST16C2451 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART
ST16C2550 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART WITH 16-BYTE FIFO
ST16C2550_04 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART WITH 16-BYTE FIFO
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