參數(shù)資料
型號: ST16C2450IJ44
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.97V TO 5.5V DUART
中文描述: 2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 3/29頁
文件大?。?/td> 315K
代理商: ST16C2450IJ44
á
REV. 4.0.0
ST16C2450
2.97V TO 5.5V DUART
3
PIN DESCRIPTIONS
ORDERING INFORMATION
P
ART
N
UMBER
P
ACKAGE
O
PERATING
T
EMPERATURE
R
ANGE
D
EVICE
S
TATUS
ST16C2450CP40
40-Lead PDIP
0°C to +70°C
Active. See the ST16C2450CQ48 for new designs.
ST16C2450CJ44
44-Lead PLCC
0°C to +70°C
Active
ST16C2450CQ48
48-Lead TQFP
0°C to +70°C
Active
ST16C2450IP40
40-Lead PDIP
-40°C to +85°C
Active. See the ST16C2450IQ48 for new designs.
ST16C2450IJ44
44-Lead PLCC
-40°C to +85°C
Active
ST16C2450IQ48
48-Lead TQFP
-40°C to +85°C
Active
Pin Description
N
AME
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
29
30
31
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
3
2
1
48
47
46
45
44
IO
Data bus lines [7:0] (bidirectional).
IOR#
24
19
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
IOW#
20
15
I
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CSA#
16
10
I
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
CSB#
17
11
I
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
INTA
33
30
O
UART channel A Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTA is set to the
active mode and OP2A# output to a logic 0 when MCR[3] is set to a
logic 1. INTA is set to the three state mode and OP2A# to a logic 1
when MCR[3] is set to a logic 0 (default).
相關PDF資料
PDF描述
ST16C2450IP40 2.97V TO 5.5V DUART
ST16C2450IQ48 2.97V TO 5.5V DUART
ST16C2451 2.97V TO 5.5V DUART
ST16C2552CJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552IJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
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