參數(shù)資料
型號(hào)： ST16C2450CJ44
廠商： STARTECH SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 2.97V TO 5.5V DUART
中文描述： 2 CHANNEL(S), 448K bps, SERIAL COMM CONTROLLER, PQCC44
文件頁(yè)數(shù)： 18/29頁(yè)
文件大?。?/td> 315K
代理商： ST16C2450CJ44
ST16C2450
2.97V TO 5.5V DUART
á
REV. 4.0.0
18
LSR[2]: Receive Data Parity Error Flag
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR. If the LSR interrupt is enabled (IER
bit-2), an interrupt will be generated when the character is in the RHR.
LSR[3]: Receive Data Framing Error Flag
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. If the LSR interrupt is enabled (IER bit-2), an interrupt will be
generated when the character is in the RHR.
LSR[4]: Receive Break Flag
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). The
break indication remains until the RX input returns to the idle condition, “mark” or logic 1. If the LSR interrupt
is enabled (IER bit-2), an interrupt will be generated when the character is in the RHR.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when the data byte is transferred from the
transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data
loading to the transmit holding register by the host.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR
contains a data character.
LSR[7]: Reserved
4.8
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits are
set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general purpose
inputs/outputs when they are not used with modem signals.
MSR[0]: Delta CTS# Input Flag
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
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參數(shù)描述
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ST16C2450CJ44TR 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
ST16C2450CJ44TR-F 制造商:Exar Corporation 功能描述:UART 2-CH 1Byte FIFO 3.3V/5V 44-Pin PLCC T/R 制造商:Exar Corporation 功能描述:ST16C2450CJ44TR-F
ST16C2450CP40 功能描述:UART 接口集成電路 DUAL UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
ST16C2450CP40-F 功能描述:UART 接口集成電路 DUAL UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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