參數(shù)資料
型號: ST16C1551CQ48
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.97V TO 5.5V UART WITH 16-BYTE FIFO
中文描述: 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁數(shù): 36/37頁
文件大?。?/td> 428K
代理商: ST16C1551CQ48
ST16C1550/51
REV. 4.2.0
á
2.97V TO 5.5V UART WITH 16-BYTE FIFO
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
F
EATURES
.....................................................................................................................................................1
A
PPLICATIONS
................................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
............................................................................................................................................................. 1
F
IGURE
2. ST16C1550 P
INOUTS
..................................................................................................................................................... 2
F
IGURE
3. ST16C1551 P
INOUTS
..................................................................................................................................................... 3
ORDERING
INFORMATION
.................................................................................................................................4
PIN DESCRIPTIONS .........................................................................................................5
DATA BUS INTERFACE .............................................................................................................................................5
MODEM OR SERIAL I/O INTERFACE........................................................................................................................5
ANCILLARY SIGNALS................................................................................................................................................6
1.0 PRODUCT DESCRIPTION .....................................................................................................................7
Enhanced Features .....................................................................................................................................................7
.....................................................................................................................................................................................7
Data Rate ....................................................................................................................................................................7
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................8
2.1 INTERNAL REGISTERS ................................................................................................................................... 8
2.2 DMA MODE ....................................................................................................................................................... 8
2.3 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK ......................................................................................... 8
T
ABLE
1: TXRDY
AND
RXRDY B
ITS
IN
FIFO
AND
DMA M
ODE
........................................................................................................ 8
2.4 PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................. 9
F
IGURE
4. T
YPICAL
OSCILLATOR
CONNECTIONS
................................................................................................................................. 9
2.5 TRANSMITTER ............................................................................................................................................... 10
2.5.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 10
2.5.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................. 10
T
ABLE
2: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
...................................................................... 10
2.5.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 11
2.6 RECEIVER ...................................................................................................................................................... 11
2.6.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 11
F
IGURE
5. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
.............................................................................................................. 11
2.7 SPECIAL (ENHANCED FEATURE) MODE .................................................................................................... 12
2.7.1 SOFT RESET .............................................................................................................................................................. 12
2.7.2 POWER DOWN MODE ............................................................................................................................................... 12
2.7.3 TXRDY AND RXRDY BITS ......................................................................................................................................... 12
2.8 INTERNAL LOOPBACK ................................................................................................................................ 12
F
IGURE
6. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
.................................................................................................................... 12
F
IGURE
7. I
NTERNAL
L
OOPBACK
..................................................................................................................................................... 13
3.0 UART INTERNAL REGISTERS ...........................................................................................................14
T
ABLE
3: ST16C155X UART INTERNAL REGISTERS ............................................................................................................... 14
T
ABLE
4: INTERNAL REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1......................................... 15
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................16
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 16
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 16
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 16
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 16
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 16
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 17
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 17
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 17
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 18
T
ABLE
5: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
....................................................................................................................... 18
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 19
T
ABLE
6: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
.............................................................................................. 19
T
ABLE
7: P
ARITY
SELECTION
.......................................................................................................................................................... 20
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 21
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 22
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 23
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 23
T
ABLE
8: UART RESET CONDITIONS........................................................................................................................................ 24
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