參數(shù)資料
型號: ST16C1551CJ28
廠商: STARTECH SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 2.97V TO 5.5V UART WITH 16-BYTE FIFO
中文描述: 1 CHANNEL(S), 448K bps, SERIAL COMM CONTROLLER, PQCC28
文件頁數(shù): 19/37頁
文件大?。?/td> 428K
代理商: ST16C1551CJ28
á
REV. 4.2.0
ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
19
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select
These 2 bits are only active when IER bit-5 is a ‘1’.
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load.
Table 6
shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
Table 6
shows the complete selections.
4.6
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
Line Control Register (LCR) - Read/Write
T
ABLE
6: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
FCR
B
IT
-7
FCR
B
IT
-6
FCR
B
IT
-5
FCR
BIT
-4
R
ECEIVE
T
RIGGER
L
EVEL
T
RANSMIT
T
RIGGER
L
EVEL
0
0
1
1
0
1
0
1
1
4
8
14
0
0
1
1
0
1
0
1
1
4
8
14
BIT-1
BIT-0
W
ORD
LENGTH
0
0
5 (default)
0
1
6
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