參數(shù)資料
型號(hào)： ST16C1550
廠商： Exar Corporation
英文描述： 2.97V TO 5.5V UART WITH 16-BYTE FIFO
中文描述： 2.97V至5.5V的UART具有16字節(jié)FIFO
文件頁(yè)數(shù)： 22/37頁(yè)
文件大?。?/td> 428K
代理商： ST16C1550
ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
á
REV. 4.2.0
22
Logic 1 = Enable local loopback mode, see loopback section and
Figure 7
.
MCR[6:5]: Reserved
MCR[7]: Power Down Enable
This bit can only be accessed when IER bit-5 = 1.
Logic 0 = Normal mode (default).
Logic 1 = Power down mode.
See “Power Down Mode” on page 12.
4.8
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic
1, an LSR interrupt will be generated when the character that is ready to be read from the RX FIFO has an
error (parity, framing, overrun, break).
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Error Flag
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
Logic 0 = No parity error (default).
Logic 1 = Parity error. The received character in RHR does not have correct parity information and is
suspect. This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
Logic 0 = No framing error (default).
Logic 1 = Framing error. The received character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Error Tag
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or logic 1.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
Logic 0 = No FIFO error (default).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST16C1550_05 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO
ST16C1550CJ28 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
ST16C1550CJ28-F 功能描述:UART 接口集成電路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
ST16C1550CJ28-F 制造商:Exar Corporation 功能描述:IC SGL UART 1.5MBPS 5.5V 28-PLCC
ST16C1550CJ28TR-F 功能描述:UART 接口集成電路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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