參數(shù)資料
型號(hào)： ST16C1451CJ28
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 2.97V TO 5.5V UART
中文描述： 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC28
封裝： PLASTIC, LCC-28
文件頁(yè)數(shù)： 20/32頁(yè)
文件大?。?/td> 355K
代理商： ST16C1451CJ28
ST16C1450/51
2.97V TO 5.5V UART
á
REV. 4.2.0
20
LSR[2]: Receive Data Parity Error Tag
Logic 0 = No parity error (default).
Logic 1 = Parity error. The received character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
Logic 0 = No framing error (default).
Logic 1 = Framing error. The received character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Error Tag
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time).
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the data byte is
transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently
with the data loading to the transmit holding register by the host.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR
contains a data character.
LSR[7]: Reserved
4.8
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.
MSR[0]: Delta CTS# Input Flag
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST16C1451CP28 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART
ST16C1451CQ48 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART
ST16C1451IJ28 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART
ST16C1451IP28 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART
ST16C1451IQ48 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART
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