參數(shù)資料
型號(hào)： ST16C1450CQ48
廠商： STARTECH SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 2.97V TO 5.5V UART
中文描述： 1 CHANNEL(S), 448K bps, SERIAL COMM CONTROLLER, PQFP48
文件頁(yè)數(shù)： 19/32頁(yè)
文件大?。?/td> 355K
代理商： ST16C1450CQ48
á
REV. 4.2.0
ST16C1450/51
2.97V TO 5.5V UART
19
MCR[2]: OP1# Output/Soft Reset
OP1# is not available as an output pin on the 145X. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
Logic 0 = OP1# output (RI# input) is at logic 1 (default).
Logic 1 = OP1# output (RI# input) is at logic 0.
In normal operation, this bit is associated with the RST (buffered reset) output pin. The logical state of the RST
pin will follow exactly the logical state of the RESET pin. When IER bit-5 = 1, soft resets from MCR bit-2 are
ORed with the state of the RESET input pin. Therefore both reset types will be seen at the RST pin. Note that
asserting MCR bit-2 does not reset the 145X.
Logic 0 = The RST output pin is a logic 0 (default).
Logic 1 = The RST output pin is a logic 1.
MCR[3]: OP2# or INT Output Enable
When not in Internal Loopback Mode:
Logic 0 = INT output is three-state (default).
Logic 1 = INT output is active high.
OP2# is not available as an output pin on the 145X. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem CD# interface signal.
Logic 0 = OP2# output (CD# input) is a logic 1 (default).
Logic 1 = OP2# output (CD# input) is a logic 0.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Figure 7
.
MCR[6:5]: Reserved
MCR[7]: Power Down Enable
This bit can only be accessed when IER bit-5 = 1.
Logic 0 = Normal mode (default).
Logic 1 = Power down mode.
See “Power Down Mode” on page 11.
4.7
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic
1, an LSR interrupt will be generated when the character that is in the RHR has an error (parity, framing,
overrun, break).
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register (default).
Logic 1 = Data has been received and is saved in the receive holding register.
LSR[1]: Receiver Overrun Error Flag
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while there is data in the RHR. In this case the previous data in the receive shift
register is overwritten. Note that under this condition the data byte in the receive shift register is not
transferred into the RHR, therefore the data in the RHR is not corrupted by the error.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ST16C1450CQ48TR-F 制造商:Exar Corporation 功能描述:UART 1-CH 1Byte FIFO 3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:ST16C1450CQ48TR-F
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