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參數(shù)資料
| 型號： | SSTUB32S868DHLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGIST BUFF 25BIT DDR2 176BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2011 |
| 標準包裝： | 208 |
| 邏輯類型： | DDR2 的寄存緩沖器 |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 位數(shù)： | 25 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 176-CABGA（6x15） |
| 包裝： | 托盤 |
6
ICSSSTUB32S868D
Advance Information
08/14/06
Ball Assignment
Data inputs = D1-D5, D7, D9-D12, D17-D28 when C=0
Data inputs = D1-D12, D17-D20, D22, D24-D28 when C=1
Data outputs = Q1-Q5, Q7, Q9-Q12, Q17-Q28 when C=0
Data outputs = Q1-Q12, Q17-Q20, Q22, Q24-Q28 when C=1
Terminal
name
Description
Electrical
characteristics
GND
Ground
Ground input
VDD
Power supply voltage
1.8-V nominal
VREF
Input reference voltage
0.9-V nominal
CK
Positive master clock input
Differential input
CK#
Negative master clock input
C
Configuration control inputs - Register A or Register B
RST#
Asynchronous reset input – resets registers and disables VREF data
and clock differential-input receivers
CSGEN
Chip select gate enable – When high, D1-D28 inputs will be latched only
when at least one chip select input is low during the rising edge of the clock. When
low, theD1-D28 inputs will be latched and redriven on every rising edge of the clock.
LVCMOS input
LVCMOS inputs
D1-D28
Data input – clocked in on the crossing of the rising edge of CK and
the falling edge of CK#.
SSTL_18 input
DCS0#,
DCS1#
Chip select inputs – These pins initiate DRAM address/command decodes,
and as such at least one will be low when a valid address/command is
present. The Register can be programmed to redrive all D inputs
(CSGEN high) only when atleast one chip select input is low. If CSGEN,
DCS0#, and DCS1# inputs are high, D1–D28 inputs will be disabled.
SSTL_18 input
DODT0,
DODT1
The outputs of this register bit will not be suspended by the DC0# and
DCS1# control.
DCKE0,
DCKE1
The outputs of this register bit will not be suspended by the DC0# and
DCS1# control.
PAR_IN
Parity input - arrives one clock cycle after the corresponding data input.
Q1-Q28
Data outputs that are suspended by the DC0# and DCS1# control.
1.8-V CMOS outputs
QCS0#, QCS1# Data output that will not be suspended by the DC0# and DCS1# control.
1.8-V CMOS output
QODT0,
QODT1
Data output that will not be suspended by the DC0# and DCS1# control.
1.8-V CMOS output
QCKE0,
QCKE1
Data output that will not be suspended by the DC0# and DCS1# control.
1.8-V CMOS output
QERR#
Output error bit - generated one clock cycle after the corresponding data output Open-drain output
NC
No internal connection
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| SSTUB32S868DHLFT | 功能描述:IC REGIST BUFF 25BIT DDR2 176BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUB32S869BHLF | 功能描述:IC REGIST BUFF 14BIT DDR2 150BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 信號緩沖器，中繼器，分配器 系列:- 標準包裝:160 系列:- 類型:轉(zhuǎn)發(fā)器 Tx/Rx類型:以太網(wǎng) 延遲時間:- 電容 - 輸入:- 電源電壓:2.37 V ~ 2.63 V 電流 - 電源:60mA 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:托盤 其它名稱:Q5134101 |
| SSTUB32S869BHLFT | 功能描述:IC REGIST BUFF 14BIT DDR2 150BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 信號緩沖器，中繼器，分配器 系列:- 標準包裝:160 系列:- 類型:轉(zhuǎn)發(fā)器 Tx/Rx類型:以太網(wǎng) 延遲時間:- 電容 - 輸入:- 電源電壓:2.37 V ~ 2.63 V 電流 - 電源:60mA 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:托盤 其它名稱:Q5134101 |
| SSTUBF32866AHLF | 制造商:Integrated Device Technology Inc 功能描述:REGISTERED BFFR SGL 25-CH CMOS 96CABGA - Trays |
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