參數(shù)資料
型號(hào)： SST85LP1004A-M-C-LBTE
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
封裝： 12 X 24 MM, 1.30 MM HEIGHT, ROHS COMPLIANT, MO-210, LBGA-91
文件頁(yè)數(shù)： 10/35頁(yè)
文件大小： 892K
代理商： SST85LP1004A-M-C-LBTE
2009 Silicon Storage Technology, Inc.
S71412-02-000
10/09
18
4 GByte NANDrive
SST85LP1004A
Data Sheet
Word 63: Multi-word DMA Transfer Mode
This field identifies the multi-word DMA transfer modes supported by the NANDrive and indicates the
mode that is currently selected. Only one DMA mode can be selected at any given time.
Bit
Function
15-11
Reserved
10
Multi-word DMA mode 2 selected
1: Multi-word DMA mode 2 is selected and bits 8 and 9 are cleared to 0
0: Multi-word DMA mode 2 is not selected.
9
Multi-word DMA mode 1 selected
1: Multi-word DMA mode 1 is selected and 8 and 10 should be cleared to 0.
0: Multi-word DMA mode 1 is not selected.
8
Multi-word DMA mode 0 selected
1: Multi-word DMA mode 0 is selected and bits 9 and 10 are cleared to 0.
0: Multi-word DMA mode 0 is not selected.
7-3
Reserved
2
Multi-word DMA mode 2 supported
1: Multi-word DMA mode 2 and below are supported and Bits 0 and 1 are set to 1.
1
Multi-word DMA mode 1 supported
1: Multi-word DMA mode 1 and below are supported.
0
Multi-word DMA mode 0 supported
1: Multi-word DMA mode 0 is supported.
Word 64: Advanced PIO Data Transfer Mode
Bits [7:0] is defined as the PIO data and register transfer supported field. If this field is supported, bit 1
of word 53 shall be set to one. This field is bit significant. Any number of bits may be set to one in this
field by the device to indicate the PIO modes the device is capable of supporting. Of these bits, bits
[7:2] are Reserved for future PIO modes.
Bit
Function
0
1: NANDrive supports PIO Mode-3.
1
1: NANDrive supports PIO Mode-4.
Word 65: Minimum Multi-word DMA Transfer Cycle Time Per Word
This field defines the minimum Multi-word DMA transfer cycle time per word. This field defines, in
nanoseconds, the minimum cycle time that the NANDrive supports when performing Multi-word DMA
transfers on a per word basis. SST’s NANDrive supports up to Multi-word DMA Mode-2, so this field is
set to 120ns.
Word 66: Device Recommended Multi-word DMA Cycle Time
This field defines the NANDrive recommended Multi-word DMA transfer cycle time. This field defines,
in nanoseconds, the minimum cycle time per word during a single sector host transfer while performing
a multiple sector READ DMA or WRITE DMA command for any location on the media under nominal
conditions. If a host runs at a faster cycle rate by operating at a cycle time of less than this value, the
NANDrive may negate DMARQ for flow control. The rate at which DMARQ is negated could result in
reduced throughput despite the faster cycle rate. Transfer at this rate does not ensure that flow control
will not be used, but implies that higher performance may result. SST’s NANDrive supports up to Multi-
word DMA Mode-2, so this field is set to 120 ns.
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