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參數(shù)資料
| 型號： | SR3.3.TG |
| 元件分類： | TVS二極管 - 瞬態(tài)電壓抑制 |
| 英文描述： | 150 W, UNIDIRECTIONAL, SILICON, TVS DIODE |
| 封裝： | PLASTIC PACKAGE-4 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 93K |
| 代理商： | SR3.3.TG |
4
2003 Semtech Corp.
www.semtech.com
PROTECTION PRODUCTS
SR3.3
Data Line and Power Supply Protection Using
Vcc as reference
Data Line Protection with Bias and Power Sup-
ply Isolation Resistor
Data Line Pr
Data Line Proooootttttection Using Int
ection Using Int
ection Using Internal T
ernal T
ernal TVVVVVS Diode
S Diode
as Reference
Device Connection Options for Protection of
TTTTTw
w
wo High-Speed Data Lines
o High-Speed Data Lines
The SR3.3 TVS is designed to protect two data lines
from transient over-voltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode V
F) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 2 and 3. The nega-
tive reference (REF1) is connected at pin 1. This pin
should be connected directly to a ground plane on the
board for best results. The path length is kept as short
as possible to minimize parasitic inductance.
The positive reference (REF2) is connected at pin 4.
The options for connecting the positive reference are
as follows:
1. To protect data lines and the power line, connect
pin 4 directly to the positive supply rail (V
CC). In this
configuration the data lines are referenced to the
supply voltage. The internal TVS diode prevents
over-voltage on the supply rail.
2. The SR3.3 can be isolated from the power supply
by adding a series resistor between pin 4 and V
CC.
A value of 10k
is recommended. The internal
TVS and steering diodes remain biased, providing
the advantage of lower capacitance.
3. In applications where no positive supply reference
is available, or complete supply isolation is desired,
the internal TVS may be used as the reference. In
this case, pin 4 is not connected. The steering
diodes will begin to conduct when the voltage on
the protected line exceeds the working voltage of
the TVS (plus one diode drop).
Board Layout Considerations for ESD Protection
Board layout plays an important role in the suppression
of extremely fast rise-time ESD transients. Recall that
the voltage developed across an inductive load is
proportional to the time rate of change of current
through the load (V = L di/dt). The total clamping
voltage seen by the protected load will be the sum of
Applications Information
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