參數(shù)資料
型號(hào)： SPC5515SBMLQ66
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 27/54頁(yè)
文件大?。?/td> 0K
描述： MCU POWERPC AN15 FIXED 144-LQFP
標(biāo)準(zhǔn)包裝： 60
系列： MPC55xx Qorivva
核心處理器： e200z1
芯體尺寸： 32-位
速度： 66MHz
連通性： CAN，I²C，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 111
程序存儲(chǔ)器容量： 768KB（768K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 48K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 40x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 144-LQFP
包裝： 托盤(pán)
Electrical Characteristics
MPC5510 Microcontroller Family Data Sheet, Rev. 3
Freescale Semiconductor
33
2.9
FMPLL Electrical Characteristics
Table 14. FMPLL Electrical Specifications 1
1 V
DDSYN = 3.0V to 3.6 V, VSSSYN = 0 V, TA = TL to TH
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
1
System frequency2
-40 oC
≤ T
J ≤ 120
oC
-40 oC
≤ T
J ≤ 145
oC
2 The maximum value is without frequency modulation turned on. If frequency modulation is turned on, the maximum value
(average frequency) must be de-rated by the percentage of modulation enabled.
fsys
375
80000 3
66000
3 80 MHz is only available in the 208 pin package.
kHz
2
PLL Reference Frequency (output of predivider)
fpllref
410
MHz
3
VCO Frequency4
4 Optimum performance is achieved with the highest VCO frequency feasible based on the highest ERFD that results in the desired
PLL frequency.
fvco
192
500
MHz
4
PLL Frequency 5
-40 oC
≤ T
J ≤ 120
oC
-40 oC
≤ T
J ≤ 145
oC
5 The VCO frequency range is higher than the maximum allowable PLL frequency. The synthesizer control register 2’s enchanced
reduced frequency divider (FMPLL_SYNCR2[ERFD]) in enhanced operation mode must be programmed to divide the VCO
frequency within the PLL frequency range.
fpll
3
80 3
66
MHz
5
Loss of Reference Frequency 6
6 Loss of reference frequency is the reference frequency detected by the PLL which then transitions into self clocked mode.
fLOR
100
1000
kHz
6
Self Clocked Mode Frequency 7
7 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f
LOR.
fSCM
13
35
MHz
7
PLL Lock Time 8
8 This specification applies to the period required for the PLL to relock after changing the enhanced multiplication factor divider
(EMFD) bits in the synthesizer control register 1 (SYNCR1) in enhanced operation mode.
tlpll
—750
μs
8
Frequency un-LOCK Range
fUL
– 4.0
4.0
% fsys
9
Frequency LOCK Range
fLCK
– 2.0
2.0
% fsys
10
CLKOUT Cycle-to-cycle Jitter,9, 10
9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider set to divide-by-2.
10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
jitter + Cmod.
Cjitter
– 5
5
% fclkout
10a
CLKOUT Jitter at 10 s period 9,10, 11
11 The PLL % jitter reduces with more cycles. 10 s was picked for a reference point for LIN (100 Kbits), slower speeds will have
even less % jitter.
Cjitter
– 0.05
0.05
% fclkout
11
Frequency Modulation Depth 1% Setting 12,13
(fsysMax must not be exceeded)
12 Modulation depth selected must not result in f
sys value greater than the fsys maximum specified value.
13 These depth ranges are obtained by filtering the raw cycle-to-cycle clock frequency data to eliminate the presence of the the
normal clock jitter riding on top of the FM waveform. The allowable modulation rates are 400 kHz to 1 MHz.
Cmod
0.5
2
%fsys
12
Frequency Modulation Depth 2% Setting 12,13
(fsysMax must not be exceeded)
Cmod
13
%fsys
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