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| 型號： | SPC5200CVR400BR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 26/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 400MHZ 272-PBGA |
| 標準包裝： | 500 |
| 系列： | MPC52xx |
| 處理器類型： | 32-位 MPC52xx PowerPC |
| 速度： | 400MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 272-BBGA |
| 供應商設備封裝： | 272-PBGA（27x27） |
| 包裝： | 帶卷 (TR) |
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MPC5200B Data Sheet, Rev. 4
32
Freescale Semiconductor
NOTES:
1 tUI, tMLI, tLI indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (sender or recipient) is waiting for
the other agent to respond with a signal before proceeding.
tUI is an unlimited interlock that has no maximum time value.
tMLI is a limited time-out that has a defined minimum.
tLI is a limited time-out that has a defined maximum.
2 All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the sender shall
stop generating STROBE edges tRFS after negation of DMARDY. STROBE and DMARDY timing measurements are taken at
the connector of the sender. Even though the sender stops generating STROBE edges, the receiver may receive additional
STROBE edges due to propagation delays. All timing measurement switching points (low to high and high to low) are taken at
1.5 V.
t AZ
—
10
—
10
—
10
Maximum time allowed for output drivers to release
from being asserted or negated
A8.36
tZAH
20
—
20
—
20
—
Minimum delay time required for output drivers to
assert or negate from released state
A8.37
t
0—0—0—
A8.38
t ENV
20
70
20
70
20
70
Envelope time—from DMACK to STOP and
HDMARDY during data out burst initiation.
A8.39
t SR
—
50
—
30
—
20
STROBE to DMARDY time, if DMARDY is negated
before this long after STROBE edge, the recipient
receives no more than one additional data word.
A8.40
t RFS
—
75
—
60
—
50
Ready-to-Final STROBE time—no STROBE edges
are sent this long after negation of DMARDY.
A8.41
t RP
160
—
125
—
100
—
Ready-to-Pause time—the time recipient waits to
initiate pause after negating DMARDY.
A8.42
t IORDYZ
—
20
—
20
—
20
Pull-up time before allowing IORDY to be released.
A8.43
t ZIORDY
0
—
0
—
0
—
Minimum time drive waits before driving IORDY
A8.44
t ACK
20
—
20
—
20
—
Setup and hold times for DMACK, before assertion or
negation.
A8.45
t SS
50
—
50
—
50
—
Time from STROBE edge to negation of DMARQ or
assertion of STOP, when sender terminates a burst.
A8.46
Table 29. Ultra DMA Timing Specification (continued)
Sym
MODE 0
(ns)
MODE 1
(ns)
MODE 2
(ns)
Comment
SpecID
Min
Max
Min
Max
Min
Max
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