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參數(shù)資料
| 型號： | SP9840KN |
| 英文描述： | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| 中文描述： | 8位八路，4象限乘法，BiCMOS工藝援 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 134K |
| 代理商： | SP9840KN |
264
the specified load resistance and capacitance. The
reference inputs are useful for both AC and DC input
sources. However, series resistance into these pins
will degrade the linearity of the DAC — 50 Ohms of
series resistance can cause up to 0.5LSB of additional
integral linearity degradation for codes near zero, due
to the code–dependent input current dropping across
this error resistance. AC–coupled applications should
use the largest capacitor value (lowest series imped-
ance) which is practical, or use an external buffer to
drive the inputs.
The DAC switches function in a break–before–make
manner in order to minimize current spikes at the
reference inputs. The reference inputs can withstand
driving voltages slightly beyond the power rails with-
out harm; the gain of
±
1 at the op amps limits the
choice of V
/V
combinations if clipping is to be
avoided at very high or very low codes. Note that rail–
to–rail inputs can always be attenuated by choosing a
code nearer midscale, if clipping of the output is
undesirable.
Output Considerations
Each DAC output amplifier can easily drive 1Kohm
loads in parallel with 15pF at its rated slew rate. The
unique BiCMOS amplifier design also ensures stabil-
ity into heavily capacitive loads — up to 47,000pF.
Under these conditions, the slew rate will be limited by
the instantaneous current available for charging the
capacitance — the slew rate will be severely degraded,
and some damped ringing will occur. Especially
under heavy capacitive loading, a large, low imped-
ance local bypass capacitor will be required. A 0.047
μ
F
ceramic in parallel with a low–ESR 2.2 to 10
μ
F
tantalum are recommended for worst–case loads.
The amplifier outputs can withstand momentary
shorts to V
or ground. Continuous short circuit
operation can result in thermally induced damage,
and should be avoided.
If the input reference voltage is reduced to 0.6V, then
both the amplifier and DAC are functional at room
temperature at supply voltages as low as 2.5V. At V
= 2.7V, power dissipation is 9.3mW typical, with the
serial clock at 4MHz, or 7.0mW typical with the serial
clock gated off.
Interfacing to the SP9840/SP9843
A simple serial interface, similar to that used in a
74HC594 shift–register with output latch, has been
implemented in these products. A serial clock is used
to strobe serial data into a 12–stage shift–register at
each rising clock edge. The first four serial bits contain
the address of the DAC to be updated, MSB first. The
next 8 bits contain the binary value to be loaded into
the desired DAC, again MSB first. After the 12th serial
bit is clocked in, the LOADH line can be strobed to
latch the 8 bits of data into the data holding register for
the desired DAC. The address bits feed a decoding
network which steers the LOADH pulse to the clock
input of the desired DAC data holding register. The
output of the 12th shift–register is also buffered and
brought out as the SERIAL DATA OUT (SDO),
which can be used to cascade multiple devices, or for
data verification purposes.
The address field is set up such that DACA is ad-
dressed at 0001 (binary) and the others consecutively
through DACH at 1000(binary). Address 0000(bi-
nary) will not affect the operation of any channel, as
this combination is easily generated inadvertently at
power–up. Other no–operation addresses exist at
1001(binary) through 1111(binary). Another use for
no–operation addresses is to mask off updates of any
DAC channel in a multiple–part system with cas-
caded serial inputs and outputs. By sending a valid
address and data only to the desired channel, it is
possible to simplify the system hardware by driving
the LOADH pin at each part in parallel from a single
source.
Table 1
shows a register–level diagram of the
addresses, data, and the resulting operation.
A fourth control pin, PRESETL, can be used to
simultaneously preset all DAC data holding registers
to their mid–scale (80
) values. This will asynchro-
nously force all DAC outputs to buffer the voltages at
their respective inputs to their outputs with unity gain.
This feature is useful at power–up, as a simple resistor
to the supply and capacitor to ground can insure that
all DAC outputs start at a known voltage. For four–
channel multiplying applications, this sets the default
start–up gain to zero; only –70dB of feedthrough from
the V
(X) inputs will be present at the outputs.
Table
2
summarizes the operation of the four digital inputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP9840KS | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| SP9843 | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| SP9843BS | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| SP9843KS | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| SP9841 | 8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP9840KS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| SP9841 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC |
| SP9841BN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC |
| SP9841BS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC |
| SP9841KN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC |
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