- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385856 > SP9602KS Dual, 12-Bit, Low Power Voltage Output D/A Converter PDF資料下載
參數(shù)資料
| 型號： | SP9602KS |
| 英文描述： | Dual, 12-Bit, Low Power Voltage Output D/A Converter |
| 中文描述： | 雙通道，12位，低功耗，電壓輸出D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 194K |
| 代理商： | SP9602KS |
SP9602DS/02 SP9602 Dual, 12-Bit, Low Power Voltage Output D/A Converter
Copyright 1999 Sipex Corporation
5
bit mode, the four least significant bits (LSBs) are
connected to the four most significant bits (MSBs),
allowing an 8-bit MSB-justified interface. All data
inputs are enabled using the CS signal in both modes.
The digital inputs are designed to be both TTL and 5V
CMOS compatible.
In order to reduce the DAC full scale output sensitivity
to the large weighting of the MSB’s found in conven-
tional R-2R resistor ladders, the 3 MSB’s are decoded
into 8 equally weighted levels. This reduces the
contribution of each bit by a factor of 4, thus, reducing
the output sensitivity to mismatches in resistors and
switches by the same amount. Linearity errors and
stability are both improved for the same reasons.
Each D/A converter is separated from the data bus by
two registers, each consisting of level-triggered latches,
Figure 1
. The first register (input register) is 12-bits
wide. The input register is selected by the address input
A
and A
and is enabled by the CS and WR1 signals.
In the 8-bit mode, the enable signal to the 8 MSB’s
is disabled by a logic low on B1/B2 to allow the 4
LSB’s to be updated. The second register (DAC
register), accepts the decoded 3 MSB’s plus the 9
LSB’s. The two DAC registers are updated simulta-
neously for both DAC’s using the XFER and WR2
signals. Using the CLR and WR2 signals or the
power-on-reset, (enabled when the power is switched
on) the DAC registers are set to 1000 0000 0000 and
the DAC outputs will settle to 0V.
Using the control logic inputs, the user has full control
of address decoding, chip enable, data transfer and
clearing of the DAC’s. The control logic inputs are
level triggered, and like the data inputs, are TTL and
CMOS compatible. The truth table (
Table 2
) shows
the appropriate functions associated with the states of
the control logic inputs.
The DACs themselves are implemented with a preci-
sion thin–film resistor network and CMOS transmis-
sion gate switches. Each D/A converter is used to
convert the 12-bit input from its DAC register to a
precision voltage.
The bipolar voltage output of the
SP9602
is created
on-chip from the DAC Voltage Output (V
) by
using an operational amplifier and two feedback
resistors connected as shown in
Figure 2
. This
configuration produces a +4.5V bipolar output range
with standard offset binary coding (See
Table 1
.).
THEORY OF OPERATION
The
SP9602
consists of five main functional blocks
— the input data multiplexer, the data registers,
control logic, two 12-bit D/A converters, and two
bipolar output voltage amplifiers. The input data
multiplexer is designed to interface to either 12- or 8-
bit microprocessor data busses. The input data format
is controlled by the B1/B2 signal — a logic “1” selects
the 12-bit mode, while a logic “0” selects the 8-bit
mode. In the 12-bit mode the data is transferred to the
input registers without changes in its format. In the 8-
FEATURES
The
SP9602
is a very low power, dual version of
the popular SP9345, Quad 12-Bit Digital-to-Ana-
log Converter. This Dual, Voltage Output, 12-Bit
Digital-to-Analog Converter features
±
4.5V out-
put swings when using
±
5 volt supplies. The input
coding format used is standard offset binary. (Please
refer to
Table 1
below.)
The converter utilizes double-buffering on each of
the 12 parallel digital inputs, for easy microproces-
sor interface. Each 12-bit DAC is independently
addressable and both DACS may be simulta-
neously updated using a single XFER command.
The output settling-time is specified at 30
μ
s to full
12–bit accuracy when driving a 5Kohm, 50pF load
combination. The
SP9602
, Dual 12-Bit Digital-to-
Analog Converter is ideally suited for applications
such as ATE, process controllers, robotics, and instru-
mentation. The
SP9602
is available in 28–pin plastic
SOIC and plastic DIP packages, specified over the
commercial (0
°
C to +70
°
C) temperature range.
Table 1. Offset Binary Coding
INPUT
OUTPUT
MSB
LSB
1111
1111
1111
V
REF
- 1 LSB
V
REF
- 2 LSB
0 + 1 LSB
1111
1111
1110
1000
0000
0001
1000
0000
0000
0
0000
0000
0001
-VREF + 1 LSB
0000
0000
0000
1 LSB = 2V
REF
-V
REF
2
12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP9840 | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| SP9840BN | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| SP9840BS | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| SP9840KN | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| SP9840KS | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP9604 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Low Power Voltage Output D/A Converter |
| SP9604JP | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Low Power Voltage Output D/A Converter |
| SP9604JS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Low Power Voltage Output D/A Converter |
| SP9604KP | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Low Power Voltage Output D/A Converter |
| SP9604KS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Quad, 12-Bit, Low Power Voltage Output D/A Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復。