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參數(shù)資料
| 型號： | SP9602 |
| 英文描述： | Dual, 12-Bit, Low Power Voltage Output D/A Converter |
| 中文描述： | 雙通道，12位，低功耗，電壓輸出D / A轉換 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 194K |
| 代理商： | SP9602 |
SP9602DS/02 SP9602 Dual, 12-Bit, Low Power Voltage Output D/A Converter
Copyright 1999 Sipex Corporation
7
Figure 2. Transfer Function
calibrate a circuit, by taking full scale or zero scale
readings for both DAC’s;
Figure 3, bottom
.
Zeroing DAC Outputs
While keeping XFER pin high, the DAC outputs can
be set to zero volts two different ways. The first
involves the CLR and WR2 pins. In normal operation,
the CLR pin is tied high, thus, disabling the clear
function. By cycling WR2 and CLR through "1"—
"0"—"1" sequence, a digital code of 1000 0000 0000
is written to both DAC registers, producing a half scale
output or zero volts. The second utilizes the built in
power-on-reset. Using this feature, the
SP9602
can
be configured such that during power-up, the second
register will be digitally “zeroed”, producing a zero
volt output at each of the DAC outputs. This is
achieved by powering the unit up with XFER in a high
state. Thus, with no external circuitry, the
SP9602
can
be powered up with the analog outputs at a known,
zero volt output level.
Temporarily Forcing
Both DAC Outputs to OV
Set WRI=1, CS=1, WR2=0, XFER=0. The DAC
registers can be temporarily forced to 1000 0000 0000
by bringing the CLR pin low. This will cause the DAC
outputs to 0V, while the CLR pin remains low. When
the CLR pin is brought back high, the digital code at
the DAC registers will again appear at the DAC's
digital inputs, and the analog outputs will return to
their previous values.
V
In
–
+
V
Out
D
V
Out
=
In
D
( )
V
DAC
=
x V
In
D
4,096
V
DAC
A
CS
WR1
B1/B2
WR2
XFER
CLR
FUNCTION
0
0
1
1
X
X
1
0
1
0
X
X
1
1
1
1
X
X
X
X
X
X
X
X
1
Address DAC 1 and load input register
Address DAC 1 and load 4 LSBs
Address DAC 2 and load input register
Address DAC 2 and load 4 LSBs
Transfer data from input registers to DAC registers
Temporarily force both DAC output voltages to
OV, while CLR is low.
Sets all DAC output voltages to 0V
Invalid state with any other control line active
Invalid state with any other control line active
**
1
**
1
0
0
X
X
X
X
1
X
X
X
1
X
X
X
1
X
X
X
X
X
X
X = Don’t care; ** = Don’t care; however, CS and WR1 = 1 will inhibit changes to the input registers.
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| SP9602KS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Dual, 12-Bit, Low Power Voltage Output D/A Converter |
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