參數(shù)資料
型號(hào): SP674AS
元件分類: ADC
英文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28
封裝: 0.600 INCH, CERDIP-28
文件頁(yè)數(shù): 4/14頁(yè)
文件大?。?/td> 204K
代理商: SP674AS
14
STAND–ALONE MODE TIMING CHARACTERISTICS
Typical @ 25C, V
CC= +15V or +12V, VLOGIC = +5V, VEE =0V, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
tHRL Low R/C Pulse Width 2
50
ns
tDS
STS Delay from R/C 2
200
ns
tHDR Data Valid After R/C Low 2
25
ns
tHS
STS Delay After Data Valid 2
300
1000
ns
tHRH High R/C Pulse Width
150
ns
tDDR Data Access Time
150
ns
NOTES:
1.
Parameters guaranteed by design and sample tested.
2.
Parameters 100% tested @ 25C on special orders.
Figure 9. Low Pulse for R/C — Outputs Enabled After Conversion
R/C
STS
DB11–DB0
tHRL
DATA VALID
tDS
DATA VALID
tC
tHS
tHDR
Figure 10. High Pulse For R/C — Outputs Enabled While R/C is High, Otherwise High Impedance
R/C
STS
DB11–DB0
DATA VALID
tDS
tC
tHRH
HIGH–Z
tDDR
tHDR
相關(guān)PDF資料
PDF描述
SP674AT/883 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28
SP674AT 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28
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