參數(shù)資料
型號: SP6138ER1-L
廠商: EXAR CORP
元件分類: 穩(wěn)壓器
英文描述: 2 A SWITCHING CONTROLLER, 2800 kHz SWITCHING FREQ-MAX, QCC16
封裝: 3 X 3 MM, LEAD FREE, MO-220VEED-4, QFN-16
文件頁數(shù): 5/17頁
文件大?。?/td> 958K
代理商: SP6138ER1-L
3
Oct 24-06 Rev J
SP638 Synchronous Buck Controller
2006 Sipex Corporation
low forward voltage. The reverse voltage
across the diode is equal to input voltage,
and the diode must be able to handle the
peak current equal to the maximum load
current.
The power dissipation of the Schottky diode
is determined by:
PDIODE = 2 VF Iout TNOL FS
where:
TNOL = non-overlap time between GH and GL.
VF = forward voltage of the Schottky diode.
Loop Compensation Design
The open loop gain of the whole system can
be divided into the gain of the error ampli-
fier, PWM modulator, buck converter output
stage, and feedback resistor divider. In or-
der to cross over at the selected frequency
FCO, the gain of the error amplifier must
compensate for the attenuation caused by
the rest of the loop at this frequency. The
goal of loop compensation is to manipulate
loop frequency response such that its gain
crosses over 0db at a slope of -20db/dec.
The first step of compensation design is
to pick the loop crossover frequency. High
crossover frequency is desirable for fast
transient response, but often jeopardizes
the system stability. Crossover frequency
should be higher than the ESR zero but
less than 1/5 of the switching frequency.
The ESR zero is contributed by the ESR
associated with the output capacitors and
can be determined by:
z(Esr) =
2π Cout REsr
The next step is to calculate the complex
conjugate poles contributed by the LC out-
put filter,
p(Lc) =
.
2π
L COUT
When the output capacitors are of a Ceramic
Type,theSP6138EvaluationBoardrequires
aTypeIIIcompensationcircuittogiveaphase
boostof180°inordertocounteracttheeffects
of an under damped resonance of the output
filter at the double pole frequency.
APPLICATION INFORMATION
(SRz2Cz2+1)(SR1Cz3+1)
(SRESRCOUT+ 1)
[S^2LC
OUT+S(RESR+RDC) COUT+1]
VIN
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
VRAMP_PP
VOUT
(Volts)
+
_
VREF
(Volts)
Notes: R
ESR = Output Capacitor Equivalent Series Resistance.
R
DC = Output Inductor DC Resistance.
V
RAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> R
ESR & RDC
R2
VREF
(R1 + R2)
or
VOUT
VFBK
(Volts)
Type III Voltage Loop
Compensation
G
AMP (s) Gain Block
PWM Stage
G
PWM Gain
Block
Output Stage
G
OUT (s) Gain
Block
Voltage Feedback
G
FBK Gain Block
Figure 5: SP6138 Voltage Mode Control Loop with Loop Dynamic
Definitions:
REsr = Output Capacitor Equivalent Series Resistance
Rdc = Output Inductor DC Resistance
Vramp _ pp = SP638 internal RAMP Amplitude Peak to Peak Voltage
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