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| 型號： | SP502CM |
| 英文描述： | Multi-Mode Serial Transceiver |
| 中文描述： | 多模式串行收發(fā)器 |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 345K |
| 代理商： | SP502CM |
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Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
22
Copyright 2003 Sipex Corporation
Several other approaches for driving the RDEC
and TDEC signals are possible. One approach
would use two independent 4-bit latches, one
each to drive the RDEC and TDEC pins as
separate groups. Another approach would use
one 4-bit latch, each output of the latch would
drive a corresponding pair of RDEC/TDEC
signals. For instance, RDEC
and TDEC
could
be tied together and be driven by the low order
bit of the 4-bit latch.
RL & LL Control Bit Registers
A 2-bit latch is used to allow the Processor to
program the states of the RL and LL interface
signals. This latch is necessary since most SCCs
do not support RL and LL control signals.
RI Status Bit Register
A 1-bit read register is implemented using a
tri-state buffer. This will allow the Processor to
read the state of the
RI
(Ring Indicator) inter-
face signal. This is necessary since most SCCs
do not support the
RI
interface signal.
The example interface shows the
SP502A
’s
IC(a) input tied to the EIA-530 signal TM (Test
Mode). EIA530 does not specify an
RI
signal. If
EIA-530 operation is required, the
RI
Status Bit
Register could be used to monitor the condition
of the TM signal or it could be ignored. For other
interface standards, the connector pin 25 on the
schematic could be tied to the
RI
signal through
a cable adapter arrangement. For instance, if
RS-232 operation is used, pin 25 of the connec-
tor could be tied to pin 22 of the RS-232 adapter
(circuit CE) and the
RI
Status Bit Register
then used to monitor the RS-232 signal for ring
indicator.
Baud Rate Clock Source
Most SCCs require an external clock source for
operation in asynchronous and self-clocking
applications.
I/O Connector Interface
The I/O connector is wired to the
SP502A
such
that the interface represents a DTE device. As
shown, the connector is wired in an EIA-530
configuration with EIA-530 signal mnemonics.
A 25-pin connector wired to the EIA-530 speci-
fication provides pins for all interface signals
supported by the
SP502
. If the
SP502
is pro-
grammed for other physical interfaces, such as
V.35, then an adapter cable will provide the
necessary conversion from the EIA-530 pin-outs
to those required by the V.35 standard together
with its ISO-2593 connector.
Notes Regarding V.35 Operation
The user will have to provide additional resistor
networks if correct V.35 signal levels and termi-
nation impedances are required. This is neces-
sary because the
SP502
does not provide V.35
signal terminations when programmed for V.35
operation. Two approaches are possible. First, if
the
SP502
is permanently programmed to oper-
ate as V.35 only, with no other interface stan-
dard required, then the appropriate resistors can
be mounted on the PCB near the
SP502
. Second,
if the
SP502
will be programmed for a variety of
standards, then a better approach might be to
provide the resistors as part of the cable adapter
assembly used to convert from the standard
EIA-530 connector pin-outs shown in the ex-
ample to the V.35/ISO-2593 connector and
pin-outs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP503 | Multiprotocol Transceiver |
| SP503AN | Application Note |
| SP503CF | Multiprotocol Transceiver |
| SP503EB | Application Note |
| SP503EF | Multiprotocol Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP503 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Multiprotocol Transceiver |
| SP503AN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Application Note |
| SP503CF | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Application Note |
| SP503CM-L | 功能描述:總線收發(fā)器 Full Duplex RS-485 s RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SP503EB | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Application Note |
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