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參數(shù)資料

型號(hào)：	SP502
英文描述：	Multi-Mode Serial Transceiver
中文描述：	多模式串行收發(fā)器
文件頁(yè)數(shù)：	20/32頁(yè)
文件大?。?/td>	345K
代理商：	SP502

Rev. 7/21/03

SP502 Multi-Mode Serial Transceiver

20

Copyright 2003 Sipex Corporation

APPLICATION EXAMPLE

The example application that follows is a fully

configured serial I/O channel in a DTE configu-

ration. The example is comprised of the follow-

ing functional elements:

Processor

SCC

SP502

Mode Select Register (R0[WR])

RL & LL Control Bit Register (R1[WR])

RI Status Bit Register (R1[RD])

Address Decode Logic

Baud Rate Clock Source

I/O Connector Interface

Each of the elements of the application example

are described below. Please refer to

Figure13

.

Processor

The example schematic shows a generic 8-bit

processor connected to a generic SCC. The

processor is also connected to three registers.

The registers are described in further detail

below.

Address Decode Logic

The address decode logic is connected to the

Processor control and address busses and pro-

vides the logic necessary to decode the I/O read

and write operations for the SCC, Mode Select

Register, RL and LL Control Bit Register and

the RI Status Bit Register.

SCC

The SCC provides the I/O functions for a single

serial channel. The SCC is connected to the

Processor I/O bus and is programmed by the

user software. The SCC’s TTL-level serial I/O

pins are connected to the corresponding

TTL-level serial I/O pins on the

SP502

.

SP502

The

SP502

provides buffering and translation

from TTL levels to the selected physical level

interface standard, such as RS-232, V.35, etc.

The physical level interface pins are connected

to a standard 25 pin D-subminiature connector

wired in a DTE configuration with the pin as-

signments corresponding to the EIA-530 speci-

fication. This choice was purely arbitrary. How-

ever, it provides all the necessary signals to

support standards other than EIA-530, such as

V.35, RS-232, RS-449, etc. with an appropriate

cable adapter.

The

SP502

driver and receiver modes are inde-

pendently configured by programming the

SP502

’s RDEC and TDEC input pins. In the

example, the pins are driven by the Mode Select

Register with a programmed value stored by the

user’s software.

Since the

SP502

is shown in a DTE configura-

tion, the example assumes that any synchronous

interface clocking will be provided by the at-

tached DCE device. Consequently, the ST/TT

pin is tied to +5V, thus causing the

SP502

to

receive the transmit clock on the TT(a) and

TT(b) input pins and output the transmit clock to

the SCC on the RxT output pin. The receive

clock is input to the

SP502

on the RT(a) and

RT(b) pins and output to the SCC on the RxC

pin.

Mode Select Register

The mode select register is an 8-bit latch at-

tached to the Processor data bus. The Processor,

under user-software control, can program the

Mode Select Register with the appropriate val-

ues to select the

SP502

’s driver and receiver

modes.

The table shown on the schematic below the

register lists the values for programming the

register to drive the RDEC and TDEC pins on

the

SP502

for the desired physical level inter-

face. The receivers and drivers can be pro-

grammed independently, but in this example the

Mode Select Register must be programmed with

both the RDEC and TDEC values at the same

time. This is because the RDEC and TDEC pins

are driven from the same 8-bit latch.

Note that selecting modes for TDEC that are

shown in the table as undefined will result in the

drivers operating in an undefined mode and

should not be used. Likewise, selecting modes

for RDEC that are shown in the table as unde-

fined will result in indeterminate logic levels

present on the TTL outputs of the

SP502

. Unde-

fined RDEC or TDEC values should never be

programmed.

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