參數(shù)資料
型號(hào): SP485RCN-L/TR
廠商: Exar Corporation
文件頁(yè)數(shù): 6/9頁(yè)
文件大?。?/td> 0K
描述: IC TXRX RS485 HALF DUPLEX 8NSOIC
標(biāo)準(zhǔn)包裝: 2,500
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: RS485
電源電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOICN
包裝: 帶卷 (TR)
6
Exar Corporation 48720 Kato Road, Fremont CA, 94538 50-668-707 www.exar.com
SP485R_00_072309
The
SP485R is a low power RS-485 dif-
ferential transceiver. Similar to the SP485,
the
SP485R contains a half-duplex driver
and receiver with tri-state control. However,
the
SP485R is intended for increased con-
nections on a single bus compared to the
original RS-485 specifcation.
The RS-485 standard is ideal for multi-drop
applications where one bus can contain
many drivers and/or receivers.The RS-485
standard implementation allows up to 32
transceivers to be connected on to the data
bus. RS-485 is also specified for driving
higher speeds over long cable lengths of
up to 4000 feet. The
SP485R exceeds the
standard by allowing up to 400 receivers to
share the bus
DRIVERS
The driver output complies with the RS-
485 electrical characteristics as specified
by the standard. The output swings from
0V to Vcc and maintains greater than +.5V
with a 54 load attached between the two
outputs. In adhering to the RS-485 specifi-
cation, the driver outputs inherently comply
with the RS-422 standard. With a load of
100 between the two outputs, the driver
can sustain at least +2.0V.
Thedrivercontainsanenablepin(DE)which
tri-states the output when DE is logic LOW.
The outputs during the tri-state condition are
at high impedance (>100k). A logic HIGH
enables the driver for normal operation. The
driver can operate to at least 5Mbps.
RECEIVERS
The
SP485R receiver has differential in-
puts with an input sensitivity of lower than
±200mV. As mentioned above, the RS-485
specification allows up to 32 transceivers on
the same bus. The
SP485R allows over 400
transceivers on the same bus due to its high
impedance of at least 120k. This higher
capacity allows more components to be at-
tached to the same bus without degrading
the signal quality. The drivers are still able to
drive an equivalent 54 from the 320
transceivers with an input impedance of at
least 120k in parallel along with the two
125 cable termination resistors on each
end.
The receiver contains an enable pin (RE)
whichenablesthereceiverwhenalogicLOW
is asserted. A logic HIGH will tri-state the
receiver output and the inputs will maintain
at least 120k impedance. The reciever can
operate to at least Mbps
The receiver also contains a fail-safe
feature which outputs a logic HIGH when
the inputs are open as in a disconnected
cable.
DESCRIPTION
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