Since both V+ and V
參數(shù)資料
型號: SP332CT-L/TR
廠商: Exar Corporation
文件頁數(shù): 9/11頁
文件大?。?/td> 0K
描述: IC TXRX RS232/485 SRL 28WSOIC
標(biāo)準(zhǔn)包裝: 1,500
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 4/4
規(guī)程: RS232,RS485
電源電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 帶卷 (TR)
7
Exar Corporation 48720 Kato Road, Fremont CA, 94538 50-668-707 www.exar.com
SP332_00_0260
Since both V+ and Vare separately gen-
erated from V
CC in a no–load condition, V+
and Vwill be symmetrical. Older charge
pump approaches that generate Vfrom
V+ will show a decrease in the magnitude
of Vcompared to V+ due to the inherent
inefficiencies in the design.
The clock rate for the charge pump typically
operates at 15kHz. The external capaci-
tors must be 0.1F with a 16V breakdown
rating.
Phase 3
— V
DD charge storage — The third phase
of the clock is identical to the first phase
— the charge transferred in C
produces
–5V in the negative terminal of C
, which
is applied to the negative side of capacitor
C
2. Since C2
+
is at +5V, the voltage potential
across C
2 is l0V.
Phase 4
— V
DD transfer — The fourth phase of the
clock connects the negative terminal of C
2
to ground and transfers the generated l0V
across C
2 to C4, the VDD storage capacitor.
Again, simultaneously with this, the positive
side of capacitor C
is switched to +5V and
the negative side is connected to ground,
and the cycle begins again.
+10V
GND
-10V
a) C2+
b) C2-
Figure 7. Charge Pump Waveforms
VCC = +5V
–5V
+5V
VSS Storage Capacitor
VDD Storage Capacitor
C1
C2
C3
C4
+
Figure 8. Charge Pump Phase 1.
VCC = +5V
–10V
VSS Storage Capacitor
VDD Storage Capacitor
C1
C2
C3
C4
+
Figure 10. Charge Pump Phase 2.
VCC = +5V
–5V
+5V
–5V
VSS Storage Capacitor
VDD Storage Capacitor
C1
C2
C3
C4
+
Figure 9. Charge Pump Phase 3.
VCC = +5V
+10V
VSS Storage Capacitor
VDD Storage Capacitor
C1
C2
C3
C4
+
Figure 11. Charge Pump Phase 4.
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