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參數(shù)資料
| 型號： | SP3222EEY-L/TR |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 23/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX RS232 ESD TRUE 20TSSOP |
| 產(chǎn)品變化通告： | Packaging Change 15/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | RS232 |
| 電源電壓： | 3 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SP3222EEY-L/TR-ND |
Exar Corporation 48720 Kato Road, Fremont CA, 94538 510-668-7017 www.exar.com
SP3222E/SP3232E_101_031413
9
Receivers
The Receivers convert EIA/TIA-232 levels
to TTL or CMOS logic output levels. The
SP3222Ereceivershaveaninvertingtri-state
output. These receiver outputs (RxOUT)
are tri-stated when the enable control EN =
HIGH. In the shutdown mode, the receivers
can be active or inactive. EN has no effect on
TxOUT. The truth table logic of the
SP3222E
driver and receiver outputs can be found in
Table 2.
Since receiver input is usually from a trans-
mission line where long cable lengths and
system interference can degrade the signal,
the inputs have a typical hysteresis margin
of 300mV. This ensures that the receiver
is virtually immune to noisy transmission
lines. Should an input be left unconnected,
an internal 5k pulldown resistor to ground
will commit the output of the receiver to a
HIGH state.
Table 2. SP3222E Truth Table Logic for Shutdown
and Enable Control
Figure 8. SP3222E/SP3232E Driver Loopback Test
Circuit
Charge Pump
The charge pump is an Exar-patended
design (U.S. 5,306,954) and uses a unique
approach compared to older less-efficient
designs. The charge pump still requires four
external capacitors, but uses a four-phase
voltage shifting technique to attain sym-
metrical 5.5V power supplies. The internal
power supply consists of a regulated dual
charge pump that provides output voltages
of +/-5.5V regardless of the input voltage
(Vcc) over the +3.0V to +5.5V range.
Figure 10. Loopback Test results at 235kbps
3
1
2
T
[
]
T1 IN
T1 OUT
R1 OUT
Ch1
Ch3
5.00V Ch2 5.00V M 2.50s Ch1
0V
5.00V
Figure 9. Loopback Test results at 120kbps
3
1
2
T
[
]
T1 IN
T1 OUT
R1 OUT
Ch1
Ch3
5.00V Ch2 5.00V M 5.00s Ch1
0V
5.00V
SP3222E
SP3232E
GND
TxIN
TxOUT
C1+
C1-
C2+
C2-
V+
V-
VCC
0.1F
+
C2
C5
C1
+
C3
C4
+
0.1F
LOGIC
INPUTS
VCC
5k
RxIN
RxOUT
LOGIC
OUTPUTS
EN*
*SHDN
1000pF
VCC
* SP3222E only
SHDN
EN
TxOUT
RxOUT
0
Tri-state
Active
0
1
Tri-state
1
0
Active
1
Active
Tri-state
DESCRIPTION
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