參數(shù)資料
    型號: SP3220E
    元件分類: 外設(shè)及接口
    英文描述: Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????)
    中文描述: 單電源RS232C接口線路驅(qū)動器/接收器(單電源RS232C接口線收發(fā)器(2發(fā)2收))
    文件頁數(shù): 10/18頁
    文件大?。?/td> 169K
    代理商: SP3220E
    SP3220E DS/04 SP3220E True +3.0 to +5.0V RS-232 Transceivers
    Copyright 2000 Sipex Corporation
    10
    Table 2. Truth Table Logic for Shutdown and
    Enable Control
    N
    D
    H
    S
    N
    E
    T
    U
    O
    x
    T
    T
    U
    O
    x
    R
    0
    0
    e
    T
    e
    v
    A
    0
    1
    e
    T
    e
    T
    1
    0
    e
    v
    A
    e
    v
    A
    1
    1
    e
    v
    A
    e
    T
    Receivers
    The receiver converts EIA/TIA-232 levels to
    TTL or CMOS logic output levels. The receiver
    has an inverting high-impedance output. This
    receiver output (RxOUT) is at high-impedance
    when the enable control EN = HIGH. In the
    shutdown mode, the receiver can be active or
    inactive. EN has no effect on TxOUT. The truth
    table logic of the
    SP3220E
    driver and receiver
    outputs can be found in
    Table 2
    .
    Since receiver input is usually from a transmission
    line where long cable lengths and system
    interference can degrade the signal, the inputs
    have a typical hysteresis margin of 300mV.
    This ensures that the receiver is virtually
    immune to noisy transmission lines. Should an
    input be left unconnected, a 5k
    pulldown
    resistor to ground will commit the output of the
    receiver to a HIGH state.
    Charge Pump
    The charge pump is a
    Sipex
    –patented design
    (U.S. 5,306,954) and uses a unique approach
    compared to older less–efficient designs. The
    charge pump still requires four external
    capacitors, but uses a four–phase voltage shifting
    technique to attain symmetrical 5.5V power
    supplies. The internal power supply consists of
    a regulated dual charge pump that provides
    output voltages 5.5V regardless of the input
    voltage (V
    CC
    ) over the +3.0V to +5.5V range.
    In most circumstances, decoupling the power
    supply can be achieved adequately using a 0.1
    μ
    F
    bypass capacitor at C5 (refer to
    Figures 5
    ).
    In applications that are sensitive to power-
    supply noise, decouple V
    to ground with a
    capacitor of the same value as charge-pump
    capacitor C1. Physically connect bypass
    capacitors as close to the IC as possible.
    The charge pumps operate in a discontinuous
    mode using an internal oscillator. If the output
    voltages are less than a magnitude of 5.5V, the
    charge pumps are enabled. If the output voltage
    exceed a magnitude of 5.5V, the charge pumps
    are disabled. This oscillator controls the four
    phases of the voltage shifting. A description of
    each phase follows.
    Phase 1
    — V
    charge storage — During this phase of
    the clock cycle, the positive side of capacitors
    C
    and C
    are initially charged to V
    . C
    switched to GND and the charge in C
    transferred to C
    the voltage potential across capacitor C
    2
    is now
    2 times V
    CC
    .
    +
    is then
    is
    . Since C
    +
    is connected to V
    ,
    Phase 2
    — V
    transfer — Phase two of the clock
    connects the negative terminal of C
    to the V
    SS
    storage capacitor and the positive terminal of C
    2
    to GND. This transfers a negative generated
    voltage to C
    . This generated voltage is
    regulated to a minimum voltage of -5.5V.
    Simultaneous with the transfer of the voltage to
    C
    , the positive side of capacitor C
    is switched
    to V
    CC
    and the negative side is connected to GND.
    Phase 3
    — V
    charge storage — The third phase of the
    clock is identical to the first phase — the charge
    transferred in C
    produces –V
    in the negative
    terminal of C
    , which is applied to the negative
    side of capacitor C
    . Since C
    voltage potential across C
    2
    is 2 times V
    CC
    .
    +
    is at V
    CC
    , the
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