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參數(shù)資料
| 型號： | SP320ACF |
| 元件分類： | RS-232 |
| 英文描述： | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| 中文描述： | 5V的高速RS - 232收發(fā)器與0.1uF電容 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 647K |
| 代理商： | SP320ACF |
5
Rev:A Date: 1/27/04 SP320 Complete +5V-Only V.35 Interface with RS-232 (V.28) Control Lines Copyright 2004 Sipex Corporation
Phase 4
-Vdd transfer- The fourth phase of the clock
connects the negative terminal of C2 to ground
and transfers the generated +10V across C2 to
C4, the Vdd storage capacitor. Again, simulta-
neously with this, the positive side of capacitor
C1 is switched to +5V and the negative side is
connected to ground, and the cycle begins again.
Since both V+ and V- are separately generated
from Vcc in a no load condition, V+and V- will
be symmetrical. Older charge pump approaches
that generate V- from V+ will show a decrease
in the magnitude of V- compared to V+ due to
the inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors must
be 0.1
μ
F with a 16V breakdown rating.
Shutdown Mode
The
SP320
can be put into a low power
shutdown mode by bringing both TS000 (pin 3)
and ENV35 (pin 9) low. In shutdown mode, the
SP320
will draw less than 2mA of supply
current. For normal operation, both pins should
be connected to +5V.
External Power Supplies
For applications that do not require +5V only,
external supplies can be applied at the V+ and
V- pins. The value of the external supply
voltages must be no greater than
±
10V. The
current drain from the
±
10V supplies is used for
the RS-232 drivers. For the RS-232 driver the
current requirement will be 3.5mA per driver.
It is critical the external power supplies provide
a power supply sequence of : +10V, +5V, and
then -10V.
Applications Information
The
SP320
is a single chip device that can
implement a complete V.35 interface. Three (3)
V.35 drivers and three (3) V.35 receivers are
used for clock and data signals and four (4)
RS-232 (V.28) drivers and four (4) RS-232
(V.28) receivers can be used for the control
signals of the interface. The following examples
show the
SP320
configured in either a DTE or
DCE application.
+10V
a) C
2
+
GND
GND
b) C
2
–
–10V
Figure 1. Charge Pump Waveforms
Figure 1a
shows the waveform found on the
positive side of capacitor C2, and
Figure 1b
shows the negative side of capacitor C2. There
is a free-running oscillator that controls the four
phases of the voltage shifting. A description of
each phase follows.
Phase 1
-Vss charge storage- During this phase of the
clock cycle, the positive side of capactors C1
and C2 are initially charged to +5V. C1+ is then
switched to ground and the charge in C1- is
transferred to C2-. Since C2+ is connected to
+5V, the voltage potential across capacitor C2 is
now 10V.
Phase 2
-Vss transfer- Phase two of the clock connects
the negative terminal of C2 to the Vss storage
capacitor and the positive terminal of C2 to
ground, and transfers the generated -10V to C3.
Simultaneously, the positive side of capacitor
C1 is switched to +5V and the negative side is
connected to ground.
Phase 3
-Vdd charge storage- The third phase of the
clock is identical to the first phase- the trans-
ferred charge in C1 produces -5V in the negative
terminal of C1, which is applied to the negative
side of capacitor C2. Since C2+ is at +5V, the
voltage potential across C2 is +10V.
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