參數(shù)資料
型號(hào)： SN75LVDS32DG4
廠商： TEXAS INSTRUMENTS INC
元件分類： Buffer和線驅(qū)動(dòng)
英文描述： QUAD LINE RECEIVER, PDSO16
封裝： GREEN, PLASTIC, SOIC-16
文件頁(yè)數(shù)： 6/18頁(yè)
文件大小： 381K
代理商： SN75LVDS32DG4
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
100
100
100
(see Note B)
100
VCC
See Note C
≈3.6 V
0.1
F
(see Note A)
1N645
(2 places)
0.01
F
5 V
NOTES: A. Place a 0.1
F Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The
capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C. Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 10. Operation With 5-V Supply
related information
IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at
www.ti.com
for more information.
For more application guidelines, please see the following documents:
D Low-Voltage Differential Signalling Design Notes (TI literature SLLA014)
D Interface Circuits for TIA/EIA-644 (LVDS) (TI literature SLLA038)
D Reducing EMI with LVDS (TI literature SLLA030)
D Slew Rate Control of LVDS Circuits (TI literature SLLA034)
D Using an LVDS Receiver with RS-422 Data (TI literature SLLA031)
D Evaluating the LVDS EVM (TI literature SLLA033)
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