- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98123 > SN74LVC1T45DCKRG4 (TEXAS INSTRUMENTS INC) LVC/LCX/Z SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO6 PDF資料下載
參數(shù)資料
| 型號： | SN74LVC1T45DCKRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO6 |
| 封裝： | GREEN, PLASTIC, SC-70, 6 PIN |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 878K |
| 代理商： | SN74LVC1T45DCKRG4 |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
Enable Times
SCES515I – DECEMBER 2003 – REVISED MAY 2009 ..................................................................................................................................................... www.ti.com
The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to
SYSTEM-1.
STATE
DIR CTRL
I/O-1
I/O-2
DESCRIPTION
1
H
Out
In
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The
2
H
Hi-Z
bus-line state depends on pullup or pulldown.(1)
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or
3
L
Hi-Z
pulldown.(1)
4
L
Out
In
SYSTEM-2 data to SYSTEM-1
(1)
SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 3. Bidirectional Logic Level-Shifting Application
Calculate the enable times for the SN74LVC1T45 using the following formulas:
t
PZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
t
PZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
t
PZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
t
PZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74LVC1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
14
Copyright 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1T45
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74LVC2244ADGVRG4 | LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| SN74LVC2244APWE4 | LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| SN74LVC244ARGYRG4 | LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PQCC20 |
| SN74LVC245AIPWREP | LVC/LCX/Z SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20 |
| SN74LVC245APW | LVC/LCX/Z SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LVC1T45DCKT | 功能描述:轉(zhuǎn)換 - 電壓電平 SNGL Bit Dual Supply Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74LVC1T45DCKTE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 SNGL Bit Dual Supply Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74LVC1T45DCKTG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 SNGL Bit Dual Supply Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74LVC1T45DPKR | 功能描述:轉(zhuǎn)換 - 電壓電平 Single Bit Dual-Sply Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74LVC1T45DRLR | 功能描述:轉(zhuǎn)換 - 電壓電平 SNGL Bit Dual Supply Bus Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。