參數(shù)資料
型號: SN74LV367ADBLE
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: LV/LV-A/LVX/H SERIES, 6-BIT DRIVER, TRUE OUTPUT, PDSO16
封裝: PLASTIC, SSOP-16
文件頁數(shù): 1/11頁
文件大?。?/td> 184K
代理商: SN74LV367ADBLE
SN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS398C – APRIL 1998 – REVISED MAY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D EPIC (Enhanced-Performance Implanted
CMOS) Process
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D 2-V to 5.5-V VCC Operation
D Support Mixed-Mode Voltage Operation on
All Ports
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD-22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
The ’LV367A devices are hex buffers and line
drivers designed for 2-V to 5.5-V VCC operation.
These devices are designed specifically to
improve both the performance and density of
3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters.
The ’LV367A devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE
and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When
OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LV367A is characterized for operation over the full military temperature range of –55
°C to 125°C. The
SN74LV367A is characterized for operation from –40
°C to 85°C.
FUNCTION TABLE
(each buffer/driver)
INPUTS
OUTPUT
OE
A
Y
L
H
L
LL
H
X
Z
32 1 20 19
910 11 1213
4
5
6
7
8
18
17
16
15
14
2A2
2Y2
NC
2A1
2Y1
1Y1
1A2
NC
1Y2
1A3
1A1
1OE
NC
1Y4
1A4
V
2OE
1Y3
GND
NC
SN54LV367A . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OE
1A1
1Y1
1A2
1Y2
1A3
1Y3
GND
VCC
2OE
2A2
2Y2
2A1
2Y1
1A4
1Y4
SN54LV367A ...J OR W PACKAGE
SN74LV367A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright
2000, Texas Instruments Incorporated
EPIC is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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