參數(shù)資料
型號: SN74LS393DR2
廠商: ON SEMICONDUCTOR
元件分類: 計數(shù)器
英文描述: LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14
封裝: PLASTIC, SOIC-14
文件頁數(shù): 4/8頁
文件大?。?/td> 212K
代理商: SN74LS393DR2
SN74LS393
http://onsemi.com
4
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
0.35
0.5
V
IOL = 8.0 mA
IIH
Input HIGH Current
20
μA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
MR
0.4
mA
VCC = MAX, VIN = 0.4 V
CP, CP0
1.6
mA
CP1
2.4
mA
IOS
Short Circuit Current (Note 2)
20
100
mA
VCC = MAX
ICC
Power Supply Current
26
mA
VCC = MAX
2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
fMAX
Maximum Clock Frequency
CP0 to Q0
25
35
MHz
CL = 15 pF
fMAX
Maximum Clock Frequency
CP1 to Q1
20
MHz
tPLH
tPHL
Propagation Delay,
CP to Q0
12
13
20
ns
tPLH
tPHL
CP to Q3
40
60
ns
tPHL
MR to Any Output
24
39
ns
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tW
Clock Pulse Width
20
ns
VCC = 5.0 V
tW
MR Pulse Width
20
ns
trec
Recovery Time
25
ns
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