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參數(shù)資料
| 型號： | SN74LS373DWR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output |
| 中文描述： | LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 209K |
| 代理商： | SN74LS373DWR2 |
SN74LS373, SN74LS374
http://onsemi.com
4
AC CHARACTERISTICS
(T
A
= 25
°
C, V
CC
= 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
LS373
LS374
Min
Typ
Max
Min
Typ
Max
f
MAX
Maximum Clock Frequency
35
50
MHz
C
L
= 45 pF,
R
L
= 667
Ω
t
PLH
t
PHL
Propagation Delay,
Data to Output
12
12
18
18
ns
t
PLH
t
PHL
Clock or Enable
to Output
20
18
30
30
15
19
28
28
ns
t
PZH
t
PZL
Output Enable Time
15
25
28
36
20
21
28
28
ns
t
PHZ
t
PLZ
Output Disable Time
12
15
20
25
12
15
20
25
ns
C
L
= 5.0 pF
AC SETUP REQUIREMENTS
(T
A
= 25
°
C, V
CC
= 5.0 V)
Symbol
Parameter
Limits
Unit
LS373
LS374
Min
Max
Min
Max
t
W
Clock Pulse Width
15
15
ns
t
s
Setup Time
5.0
20
ns
t
h
Hold Time
20
0
ns
DEFINITION OF TERMS
SETUP TIME (t
s
) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to LE transition from HIGH-to-LOW in order to
be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the LE transition from HIGH-to-LOW that the
logic level must be maintained at the input in order to ensure
continued recognition.
SN74LS373
AC WAVEFORMS
Figure 1.
t
W
t
W
LE
1.3 V
OUTPUT
D
n
t
s
t
h
t
PLH
t
PHL
Figure 2.
Figure 3.
1.3 V
1.3 V
1.3 V
OE
V
OUT
OE
V
OUT
t
PHZ
1.3 V
1.3 V
t
PZL
t
PLZ
V
OL
1.3 V
V
OH
0.5 V
t
PZH
1.3 V
1.3 V
0.5 V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74LS373M | Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output |
| SN74LS373MEL | Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output |
| SN74LS374DWR2 | Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output |
| SN74LS374M | Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output |
| SN74LS374MEL | Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LS373DWRE4 | 功能描述:閉鎖 Octal D Type Transp Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LS373DWRG4 | 功能描述:閉鎖 Octal D Type Transp Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LS373FN | 制造商:. 功能描述: |
| SN74LS373J | 制造商:Motorola 功能描述:74LS373 MOTOROLA |
| SN74LS373JTI83 | 制造商:TI 功能描述:74LS373N |
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