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參數(shù)資料
| 型號(hào)： | SN74LS195ADR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | LS SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大?。?/td> | 213K |
| 代理商： | SN74LS195ADR2 |
SN74LS195A
http://onsemi.com
5
DEFINITIONS OF TERMS
SETUP TIME(t
s
) —is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (t
rec
) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays and
Clock Pulse Width
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
CONDITIONS: MR = H
*Q
0
STATE WILL BE DETERMINED BY J AND K INPUTS.
1.3 V
1.3 V
1.3 V
1.3 V
CLOCK
OUTPUT
PE
Q
n
= P
n
Q
n
* = Q
n1
t
rel
t
rel
t
s
(L)
t
s
(H)
LOAD PARALLEL DATA
LOAD SERIAL DATA
SHIFT RIGHT
1.3 V
CONDITIONS: PE = L
PO = P
1
= P
2
= P
3
= H
CONDITIONS: MR = H
*J AND K SETUP TIME AFFECTS Q
0
ONLY
Figure 3. Setup (t
s
) and Hold (t
h
) Time for Serial Data
(J & K) and Parallel Data (P
0
, P
1
, P
2
, P
3
)
PE
J & K
P
0
P
1
P
2
P
3
CLOCK
OUTPUT*
CLOCK
CLOCK
OUTPUT
OUTPUT
t
s
(H)
t
h
(H) = 0
t
h
(L) = 0
t
h
(H) = 0
1.3V
t
s
(H)
t
h
(L) = 0
t
s
(L)
t
PHL
t
PLH
t
s
(L)
MR
t
rec
t
PHL
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
t
W
CONDITIONS: J = PE = MR = H
K = L
t
W
1.3 V
Figure 4. Setup (t
s
) and Hold (t
h
) Time for PE Input
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LS195AJ | 制造商:Motorola Inc 功能描述: |
| SN74LS195AN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: 制造商:Texas Instruments 功能描述: |
| SN74LS195AN3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS195AN84 | 制造商:Motorola 功能描述:74LS195N |
| SN74LS195AND | 制造商:Motorola Inc 功能描述:Shift Register, 16 Pin, Plastic, DIP |
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