參數(shù)資料
型號: SN74AVCH4T245PWR
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: AVC SERIES, DUAL 2-BIT TRANSCEIVER, TRUE OUTPUT, PDSO16
封裝: GREEN, PLASTIC, TSSOP-16
文件頁數(shù): 1/25頁
文件大小: 904K
代理商: SN74AVCH4T245PWR
www.ti.com
FEATURES
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCCA
1DIR
2DIR
1A1
1A2
2A1
2A2
GND
VCCB
1OE
2OE
1B1
1B2
2B1
2B2
GND
D, DGV, ORPWPACKAGE
(TOP VIEW)
RGYPACKAGE
(TOP VIEW)
RSVPACKAGE
(TOP VIEW)
1
16
8
9
2
3
4
5
6
7
15
14
13
12
11
10
1OE
2OE
1B1
1B2
2B1
2B2
1DIR
2DIR
1A1
1A2
2A1
2A2
GND
V
GND
CCB
V
CCA
1OE
2
OE
1B1
1B2
2B1
2DIR
1A1
1A2
2A1
V
CCB
1DIR
V
CCA
4
3
2
1
2B2
2A2
GND
11
10
9
12
16 15 14 13
5
6
7
8
DESCRIPTION/ORDERING INFORMATION
4-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES577D – JUNE 2004 – REVISED JUNE 2007
Control Inputs V
IH/VIL Levels Are Referenced
Max Data Rates
to VCCA Voltage
380 Mbps (1.8V to 3.3V Translation)
Fully Configurable Dual-Rail Design Allows
200 Mbps (<1.8V to 3.3V Translation)
Each Port to Operate Over the Full 1.2-V to
200 Mbps (Translate to 2.5V or 1.8V)
3.6-V Power-Supply Range
150 Mbps (Translate to 1.5V)
I/Os Are 4.6-V Tolerant
100 Mbps (Translate to 1.2V)
I
off Supports Partial Power-Down-Mode
Latch-Up Performance Exceeds 100 mA Per
Operation
JESD 78, Class II
Bus Hold on Data Inputs Eliminates the Need
ESD Protection Exceeds JESD 22
for External Pullup/Pulldown Resistors
8000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track
VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. The SN74AVCH4T245 is optimized to operate with
VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. This allows for universal
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH4T245 is designed for asynchronous communication between two data buses. The logic levels
of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the
A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A
bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port
outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or
LOW level applied to prevent excess ICC and ICCZ.
The SN74AVCH4T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance
state. The bus-hold circuitry on the powered-up side always stays active.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2004–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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