參數(shù)資料
型號(hào)： SN74ABT8952DWG4
廠商： Texas Instruments
文件頁(yè)數(shù)： 10/31頁(yè)
文件大?。?/td> 0K
描述： IC SCAN TEST DEVICE 28SOIC
標(biāo)準(zhǔn)包裝： 20
系列： 74ABT
邏輯類(lèi)型： 掃描測(cè)試設(shè)備，帶寄存總線收發(fā)器
電源電壓： 4.5 V ~ 5.5 V
位數(shù)： 8
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC
包裝： 管件
SN54ABT8952, SN74ABT8952
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS121D – AUGUST 1992 – REVISED JULY 1996
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing description
All test operations of the ’ABT8952 are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs
is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling
edge of TCK. The TAP controller is advanced through its states (as shown in Figure 1) by changing the value
of TMS on the falling edge of TCK and then applying a rising edge to TCK.
A simple timing example is shown in Figure 12. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan
and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO
is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5 details
the operation of the test circuitry during each TCK cycle.
Table 5. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
1
Test-Logic-Reset
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
2
Run-Test/Idle
3
Select-DR-Scan
4
Select-IR-Scan
5
Capture-IR
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.
6
Shift-IR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
7–13
Shift-IR
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next
TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.
14
Exit1-IR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
15
Update-IR
The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
16
Select-DR-Scan
17
Capture-DR
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.
18
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
19 – 20
Shift-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
21
Exit1-DR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
22
Update-DR
In general, the selected data register is updated with the new data on the falling edge of TCK.
23
Select-DR-Scan
24
Select-IR-Scan
25
Test-Logic-Reset
Test operation completed
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