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參數(shù)資料
| 型號： | SN74ABT8652DW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, 8-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 29/30頁 |
| 文件大?。?/td> | 506K |
| 代理商： | SN74ABT8652DW |
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SN54ABT8652, SN74ABT8652
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, then such update
occurs on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the ’ABT8652, the status
value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction register scan. It is possible to return
to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling
edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction register scan operations without loss of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ABT8652DWE4 | 功能描述:特定功能邏輯 Device w/Octal Bus Trnscvr & Register RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT8652DWG4 | 功能描述:特定功能邏輯 Scan Test Devices RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT8652DWR | 功能描述:總線收發(fā)器 Device w/Octal Bus Trnscvr & Register RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ABT8652DWRE4 | 功能描述:特定功能邏輯 Device w/Octal Bus Trnscvr & Register RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT8652DWRG4 | 功能描述:特定功能邏輯 Scan Test Devices RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
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