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| 型號(hào)： | SN65LVP16DRFRG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal D-Type 3-State Noninverting Flip-Flop; Package: SOIC-20 WB; No of Pins: 20; Container: Rail; Qty per Container: 38 |
| 中文描述： | 2.5-V/3.3-V振蕩器的增益級(jí)/緩沖器 |
| 文件頁(yè)數(shù)： | 4/15頁(yè) |
| 文件大小： | 319K |
| 代理商： | SN65LVP16DRFRG4 |
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
(1)
MAX
UNIT
SN65LVP16/17 Y AND Z OUTPUT CHARACTERISTICS
V
OYH
or
High-level output voltage
V
OZH
V
OYL
or
Low-level output voltage
V
OZL
V
OYL
or
Low-level output voltage
V
OZL
Differential output voltage magnitude,
|V
OD
|
|V
OH
– V
OL
|
I
OYZ
or I
OZZ
High-impedance output current
Q OUTPUT CHARACTERISTICS (see
Figure 1
)
V
OH
High-level output voltage
V
CC
– 1.05
V
CC
– 0.82
3.3 V; 50
from Y and Z
to V
CC
– 2 V
V
CC
– 1.83
V
CC
– 1.57
V
2.5 V; 50
from Y and Z
to V
CC
– 2 V
V
CC
– 1.88
V
CC
– 1.57
0.6
0.8
1
EN at V
CC
, V
O
= 0 V or V
CC
–1
1
μA
No load
GC Tied to GND, No load
GC Open, No load
GC Tied to V
CC
, No load
GC Tied to GND
GC Open
GC Tied to V
CC
V
CC
– 0.94
V
CC
– 1.22
V
CC
– 1.52
V
CC
– 1.82
V
V
OL
Low-level output voltage
V
300
575
860
V
O(pp)
Peak-to-peak output voltage
mV
PARAMETER
TEST CONDITIONS
MIN
TYP
(1)
340
460
MAX
460
630
UNIT
A to Q
D to Y or Z
t
PD
Propagation delay time, t
PLH
or t
PHL
See
Figure 4
ps
t
SK(P)
Pulse skew, |t
PLH
– t
PHL
|
20
80
V
CC
= 3.3 V
V
CC
= 2.5 V
t
SK(PP)
Part-to-part skew
(2)
ps
130
140
140
t
r
t
f
t
jit(per)
t
jit(cc)
t
jit(ph)
20%-to-80% differential signal rise time
20%-to-80% differential signal fall time
RMS period jitter
(3)
Peak cycle-to-cycle jitter
(4)
Intrinsic phase jitter
Propagation delay time,
high-level-to-high-impedance output
Propagation delay time,
low-level-to-high-impedance output
Propagation delay time,
high-impedance-to-high-level output
Propagation delay time,
high-impedance-to-low-level output
85
85
ps
ps
See
Figure 4
2
3
2-GHz 50%-duty-cycle square-wave input,
See
Figure 5
ps
15
23
2 GHz
0.11
ps
t
PHZ
30
t
PLZ
30
See
Figure 6
ns
t
PZH
30
t
PZL
30
(1)
(2)
Typical values are at room temperature and with a V
of 3.3 V.
Part-to-part skew is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle
pairs.
(3)
(4)
4
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| SN65LVP16DRFT | 功能描述:LVDS 接口集成電路 2.5/3.3-V Oscillator Gain Stage/Buffer RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SN65LVP16DRFTG4 | 功能描述:LVDS 接口集成電路 2.5/3.3-V Oscillator Gain Stage/Buffer RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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| SN65LVP17DRFR | 功能描述:LVDS 接口集成電路 2.5/3.3-V Oscillator Gain Stage/Buffer RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SN65LVP17DRFRG4 | 功能描述:LVDS 接口集成電路 2.5/3.3-V Oscillator Gain Stage/Buffer RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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