tRSKM is the timing margin available to allocate to the transmitter and " />
參數(shù)資料
型號(hào)： SN65LVDS94DGGRG4
廠商： Texas Instruments
文件頁(yè)數(shù)： 13/17頁(yè)
文件大?。?/td> 0K
描述： IC LVDS SERDES RECEIVER 56-TSSOP
標(biāo)準(zhǔn)包裝： 2,000
系列： 65LVDS
功能： 串行器/解串器
輸入類(lèi)型： LVDS
輸出類(lèi)型： LVTTL
輸入數(shù)： 4
輸出數(shù)： 28
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 56-TSSOP
包裝： 帶卷 (TR)
www.ti.com
(1)
tRSKM is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. It is defined by
tc
14
–ts h.
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SLLS298F – MAY 1998 – REVISED JANUARY 2006
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
VIT+
Positive-going differential input voltage threshold
100
mV
Negative-going differential input voltage
VIT-
-100
threshold(2)
VOH
High-level output voltage
IOH = -4 mA
2.4
V
VOL
Low-level output voltage
IOL = 4 mA
0.4
V
Disabled, all inputs open
280
A
Enabled, AnP at 1 V and AnM at 1.4
V,
62
84
mA
ICC
Quiescent current (average)
tc = 15.38 ns
Enabled, CL = 8 pF (5 places),
Worst-case pattern, see Figure 4,
107
mA
tc = 15.38 ns
IIH
High-level input current (SHTDN)
VIH = VCC
±20
A
IIL
Low-level input current (SHTDN)
VIL = 0 V
±20
A
IIN
Input current (A and CLKIN inputs)
0 V
≤ V
I≤ 2.4 V
±20
A
IOZ
High-impedance output current
VO = 0 V or VCC
±10
A
(1)
All typical values are VCC = 3.3 V, TA = 25°C.
(2)
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going input voltage threshold only.
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
Data setup time, D0 through D27 to
tsu
4
6
CLKOUT
CL = 8 pF
ns
Data hold time, CLKOUT to D0 through
th
4
6
D27
TA = 0°C to 85°C
490
800
Receiver input skew margin(1), see
tc = 15.38 ns (±0.2%),
tRSKM
ps
|Input clock jitter| <50 ps(2)
TA = -40°C to 0°C
390
Delay time, input clock to output clock, see
td
tc = 15.38 ns (±0.2%)
3.7
ns
tc = 15.38 + 0.75 sin (2π500E3t)±0.05 ns,
±80
Change in output clock period from cycle to
t
C(O)
ps
cycle(3)
tc = 15.38 + 0.75 sin (2≠3E6t) ±0.05 ns,
±300
ten
Enable time, SHTDN to phase lock
1
ms
tdis
Disable time, SHTDN to Off state
400
ns
tt
Output transition time (tr or tf)
CL = 8 pF
3
ns
tw
Output clock pulse duration
0.43 tc
ns
(2)
|Input clock jitter| is the magnitude of the change in the input clock period.
(3)
t
C(O) is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.
5
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