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參數(shù)資料
| 型號(hào)： | SN65LVDS94DGGR |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LVDS SERDES RECEIVER 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 65LVDS |
| 功能： | 串行器/解串器 |
| 輸入類(lèi)型： | LVDS |
| 輸出類(lèi)型： | LVTTL |
| 輸入數(shù)： | 4 |
| 輸出數(shù)： | 28 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
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APPLICATION INFORMATION
16-BIT BUS EXTENSION
SN74FB2032
8
D0–D7
8
D8–D15
SN75L0DS93
LVDS
Interface
0 To 10 Meters
(Media Dependent)
TTL
Interface
16-Bit
BTL Bus
Interface
CLK
Backplane
Bus
8
D0–D7
8 D8–D15
CLK
Backplane
Bus
TTL
Interface
16-Bit
BTL Bus
Interface
XMIT Clock
RCV Clock
SN74FB2032
SN75LV0S94
SN74FB2032
16-BIT BUS EXTENSION WITH PARITY
SLLS298F – MAY 1998 – REVISED JANUARY 2006
In a 16-bit bus application (Figure 11), TTL data and clock coming from bus transceivers that interface the
backplane bus arrive at the Tx parallel inputs of the LVDS serdes transmitter. The clock associated with the bus
is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input. The
data is then multiplexed into three different line drivers which perform the TTL to LVDS conversion. The clock is
also converted to LVDS and presented to a separate driver. This synchronized LVDS data and clock at the
receiver, which recovers the LVDS data and clock, performs a conversion back to TTL. Data is then
demultiplexed into a parallel format. An on-chip PLL synchronizes the received clock with the parallel data, and
then all are presented to the parallel output port of the receiver.
Figure 11. 16-Bit Bus Extension
In the previous application we did not have a checking bit that would provide assurance that the data crosses the
link. If we add a parity bit to the previous example, we would have a diagram similar to the one in Figure 12. The
device following the SN74FB2032 is a low cost parity generator. Each transmit-side transceiver/parity generator
takes the LVTTL data from the corresponding transceiver, performs a parity calculation over the byte, and then
passes the bits with its calculated parity value on the parallel input of the LVDS serdes transmitter. Again, the
on-chip PLL synchronizes this transmit clock with the eighteen parallel bits (16 data + 2 parity) at the input. The
synchronized LVDS data/parity and clock arrive at the receiver.
The receiver performs the conversion from LVDS to LVTTL and the transceiver/parity generator performs the
parity calculations. These devices compare their corresponding input bytes with the value received on the parity
bit. The transceiver/parity generator will assert its parity error output if a mismatch is detected.
11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN65LVDS94DGGRG4 | 功能描述:LVDS 接口集成電路 Serdes Receiver RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SN65LVDS95DGG | 功能描述:緩沖器和線路驅(qū)動(dòng)器 Serdes Transmitter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SN65LVDS95DGG | 制造商:Texas Instruments 功能描述:Transceiver IC Transceiver Type:Eia/Tia- |
| SN65LVDS95DGGG4 | 功能描述:LVDS 接口集成電路 Serdes Transmitter RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SN65LVDS95DGGR | 功能描述:LVDS 接口集成電路 Serdes Transmitter RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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