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參數(shù)資料
| 型號(hào)： | SN54HC161FK |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | 300mA, 3.0V ±1% Output Voltage, Low Dropout Voltage Regulator; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98 |
| 中文描述： | 4位同步二進(jìn)制計(jì)數(shù)器 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大?。?/td> | 202K |
| 代理商： | SN54HC161FK |
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SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
The glitch on RCO is caused because the propagation delay of the rising edge of Q
A
of the second stage is
shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, Q
A
, Q
B
, Q
C
, and Q
D
(ENT
×
Q
A
×
Q
B
×
Q
C
×
Q
D
). The resulting glitch is about 7–12 ns in duration. Figure 3 shows the condition in
which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied to
other stages. Q
, Q
C
, and Q
D
of the first and second stage are at logic one, and Q
A
of both stages are at logic
zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, Q
A
and RCO of the
first stage go high. On the rising edge of the third clock pulse, Q
A
and RCO of the first stage return to a low level,
and Q
A
of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears
because of the race condition inside the chip.
1
2
3
4
5
CLK
ENT1
QB1, QC1, QD1
QA1
RCO1, ENT2
QB2, QC2, QD2
QA2
RCO2
Glitch (7–12 ns)
Figure 3
The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock
edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the
inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (t
g
). In other words,
f
max
= 1/(t
pd
CLK-to-RCO + t
g
). For example, at 25
°
C at 4.5-V V
CC
, the clock-to-RCO propagation delay is
43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the
cascaded counters can use is 18 MHz. The following tables contain the f
clock
, t
w
, and f
max
specifications for
applications that use more than two ’HC161 devices cascaded together.
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| SN54HC161W | 300mA, 3.0V ±1% Output Voltage, Low Dropout Voltage Regulator; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500 |
| SN54HC164FK | 300mA, 5.0V +/-1% Output Voltage, Low Dropout Voltage Regulator, Pb-Free Device; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500 |
| SN54HC164W | 300mA, 2.5V +/-1% Output Voltage, Low Dropout Voltage Regulator, Pb-Free Device; Package: DPAK 4 LEAD Single Gauge Surface Mount; No of Pins: 4; Container: Rail; Qty per Container: 75 |
| SN54HC165FK | 300mA, 2.5V +/-1% Output Voltage, Low Dropout Voltage Regulator, Pb-Free Device; Package: DPAK 4 LEAD Single Gauge Surface Mount; No of Pins: 4; Container: Tape and Reel; Qty per Container: 2500 |
| SN54HC165W | 300mA, 3.0V +/-1% Output Voltage, Low Dropout Voltage Regulator; Pb Free Device; Package: DPAK 4 LEAD Single Gauge Surface Mount; No of Pins: 4; Container: Rail; Qty per Container: 75 |
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| SN54HC161J | 制造商:Texas Instruments 功能描述:Counter Single 4-Bit Sync Binary UP 16-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:SYNC 4-BIT BINARY COUNTER - Rail/Tube |
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| SN54HC166J | 制造商:Texas Instruments 功能描述: |
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