- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373442 > SN54AS109AJ (Texas Instruments, Inc.) DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET PDF資料下載
參數(shù)資料
| 型號： | SN54AS109AJ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET |
| 中文描述： | 雙JK上升沿觸發(fā)器，沒有明確的和預(yù)置觸發(fā)器 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 138K |
| 代理商： | SN54AS109AJ |
SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS198B – APRIL 1982 – REVISED AUGUST 1995
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPHZ
tPLZ
tPHL
tPLH
0.3 V
tPZL
tPZH
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
0 V
VOH
VOL
3.5 V
In-Phase
Output
0.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
CL
(see Note A)
RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR
≤
1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74AS109ADR | Quad 2-Input AND Gate; Package: SOEIAJ-14; No of Pins: 14; Container: Rail; Qty per Container: 50 |
| SN54AS10FK | TRIPLE 3-INPUT POSITIVE-NAND GATES |
| SN54ALS10AFK | TRIPLE 3-INPUT POSITIVE-NAND GATES |
| SN54AS11FK | TRIPLE 3-INPUT POSITIVE-AND GATES |
| SN54ALS11AFK | TRIPLE 3-INPUT POSITIVE-AND GATES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54AS11J | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:TRIPLE 3-INPUT AND GATE - Rail/Tube |
| SN54AS163J | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| SN54AS175AJ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54AS241AJ | 制造商:Texas Instruments 功能描述:Buffer/Line Driver 8-CH Non-Inverting 3-ST Bipolar 20-Pin CDIP Tube 制造商:Texas Instruments 功能描述:OCTAL BUFFER/DRIVER - Rail/Tube |
| SN54AS244AJ | 制造商:Texas Instruments 功能描述:Buffer/Line Driver 8-CH Non-Inverting 3-ST Bipolar 20-Pin CDIP Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。