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參數(shù)資料
| 型號(hào)： | SN54ALVTH16821 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-V/3.3-V 20-Bit Bus-Interface Flip-Flops(2.5V/3.3V 20位總線接口觸發(fā)器(三態(tài)輸出)) |
| 中文描述： | 2.5-V/3.3-V 20位總線接口正反器（2.5V/3.3V的20位總線接口觸發(fā)器（三態(tài)輸出）） |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 222K |
| 代理商： | SN54ALVTH16821 |
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078A – JULY 1996 – REVISED JULY 1996
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 3.3 V
±
0.3 V
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
VOH
VOL
1.5 V
1.5 V
3 V
0 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
, tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
P
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