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參數(shù)資料
| 型號(hào)： | SN54AC563 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal D-Type Transparent Latches With 3-State Outputs(八D鎖存器(三態(tài)輸出)) |
| 中文描述： | 八路D類透明鎖存器與三態(tài)輸出（八?鎖存器（三態(tài)輸出）） |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 165K |
| 代理商： | SN54AC563 |
SN54AC563, SN74AC563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS552A – NOVEMBER 1995 – REVISED MAY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3-State Inverting Outputs Drive Bus Lines
Directly
Full Parallel Access for Loading
Flow-Through Architecture to Optimize
PCB Layout
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
μ
m Process
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
The ’AC563 are octal D-type transparent latches
with 3-state outputs. When the latch-enable (LE)
input is high, the Q outputs follow the
complements of the data (D) inputs. When LE is
taken low, the Q outputs are latched at the inverse
logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the high-imped-
ance state. In the high-impedance state, the
outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54AC563 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74AC563 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
D
H
L
L
H
L
H
L
L
X
Q0
Z
H
X
X
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
SN54AC563 . . . J OR W PACKAGE
SN74AC563 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2
1
O
8
7
1
8
G
C
V
C
SN54AC563 . . . FK PACKAGE
(TOP VIEW)
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright
1996, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
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| SN54AC564 | Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs(八上升沿D觸發(fā)器(三態(tài)輸出)) |
| SN54AC573 | Octal D-Type Transparent Latches With 3-State Outputs(八D鎖存器(三態(tài)輸出)) |
| SN54ACT11FK | TRIPLE 3-INPUT POSITIVE-AND GATES |
| SN74ACT11DB | Low-Voltage CMOS 16-Bit Buffer, Pb-free; Package: TSSOP-48 12.5x6.1x1.1 mm; No of Pins: 48; Container: Rail; Qty per Container: 39 |
| SN54ACT11J | TRIPLE 3-INPUT POSITIVE-AND GATES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54AC564 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN54AC564_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE EDGE-TRIGGERDE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN54AC564_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN54AC564FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN54AC564J | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
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