參數(shù)資料
型號(hào): SMT4504F-172
英文描述: Four-Channel Loss-Less TrakkerTM Power Supply Manager
中文描述: 四通道無損耗TrakkerTM電源管理器
文件頁數(shù): 5/20頁
文件大?。?/td> 248K
代理商: SMT4504F-172
SMT4504
Preliminary Information
Summit Microelectronics, Inc
2071 1.1 01/07/05
5
Pin Name Type Number Function
VCTRL
C
VM
C
VCTRL
D
VM
D
IRQ
OUT
IN
OUT
IN
OUT
1
2
3
4
5
Control voltage used to track/sequence the converters
Channel C converter output or sense+ line
Control voltage used to track/sequence the converters
Channel D converter output or sense+ line
Programmable active high/low open drain latched output. Asserted when
programmed power supply is in a fault condition.
Programmable active high/low output asserted when all Fault conditions are
clear
Programmable active high/low open drain output signals when all
programmed power supplies are within the monitored limits and the MR signal
is inactive. RST has a programmable timeout period with options for
0.64/50/100/200ms.
Active low open drain I/O connected to LINK_B pin other SMT4504’s for
linked operation
Active low open drain I/O connected to LINK_A pin other SMT4504’s for
linked operation
Ground of the part
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low input internally pulled up to VDD_CAP with 75k ohm resistor
HEALTHY
OUT
6
RST
OUT
7
LINK_B
I/O
8
LINK_A
I/O
9
GND
STATUS
A
PWR
OUT
10
11
STATUS
B
OUT
12
STATUS
C
OUT
13
STATUS
D
OUT
14
SEATED#
IN
15
FS#
I/O
16
Force shutdown active low I/O used to turn off all converter enable signals.
Do not drive FS# high.
Active high I/O signals the start of the power sequencing. When asserted the
part will sequence the supplies on and when de-asserted the part will
sequence the supplies off. Do not drive PWR_ON high.
External tracking ramp reference
Bi-directional I
2
C Data line
I
2
C Clock line
I
2
C device bus address assignment pin.
I
2
C device bus address assignment pin.
I
2
C device bus address assignment pin.
Programmable active high/low write protect input. When asserted the
configuration registers are write protected and the write protect volatile
register is set.
Active low input. When asserted the RST output will be allowed to de-assert
after a reset timeout if there are no reset sources still active.
Ground of the part
Power supply of the part
PWR_ON
I/O
17
VRLINK
SDA
SCL
A0
A1
A2
WP
I/O
DATA
CLK
IN
IN
IN
IN
18
25
26
27
28
29
30
MR#
IN
31
GND
VDD
PWR
PWR
34
35
PIN DESCRIPTIONS
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