參數(shù)資料
型號(hào)： SMJ320C40TABM40/10
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 40 MHz, OTHER DSP, UUC325
封裝： TAB-325
文件頁(yè)數(shù)： 31/64頁(yè)
文件大?。?/td> 1155K
代理商： SMJ320C40TABM40/10
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H OCTOBER 1993 REVISED OCTOBER 2001
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
timing parameters for a memory read/write [(L)STRBx = 0] (see Note 6, Figure 10, and Figure 11)
NO.
320C40-40
320C40-50
320C40-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1
td(H1L-SL)
Delay time, H1 low to (L)STRBx low
0*
10
0*
10
0*
8
ns
2
td(H1L-SH)
Delay time, H1 low to (L)STRBx high
0*
10
0*
10
0*
8
ns
3
td(H1H-RWL)
Delay time, H1 high to (L)R/Wx low
0*
9
0*
9
0*
8
ns
4
td(H1L-A)
Delay time, H1 low to (L)Ax valid
0*
10
0*
9
0*
8
ns
5
tsu(D-H1L)R
Setup time, (L)Dx valid before H1 low (read)
15
10
9
ns
6
th(H1L-D)R
Hold time, (L)Dx after H1 low (read)
0
ns
7
tsu[(L)RDY-H1L]
Setup time, (L)RDYx valid before H1 low
25
20
18*
ns
8
th[H1L-(L)RDY]
Hold time, (L)RDYx after H1 low
0
ns
8.1
td(H1L-ST)
Delay time, H1 low to (L)STAT3(L)STAT0 valid
10
8
ns
9
td(H1H-RWH)W
Delay time, H1 high to (L)R/Wx high (write)
9
0*
8
ns
10
tv(H1L-D)W
Valid time, (L)Dx after H1 low (write)
16
13
ns
11
th(H1H-D)W
Hold time, (L)Dx after H1 high (write)
0
ns
12
td(H1H-A)
Delay time, H1 high to address valid on back-to-back
write cycles
13
8
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 6: For consecutive reads, (L)R/Wx stays high and (L)STRBx stays low.
6
H3
H1
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx
(L)STRBx
(L)STAT3(L)STAT0
5
3
1
2
4
8
7
8.1
Figure 10. Memory-Read-Cycle Timing [(L)STRBx = 0]
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