SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
reference documentation and data sheet scope
The SMJ320MCM41D is qualified to MIL-PRF-38535. Electrical continuity of the module is ensured through use
of IEEE-1149.1-compatible boundary-scan testing and functional checkout of local SRAM space.
KGD refers to Texas Instruments (TI
) known-good-die strategy. TI KGDs are fully tested over the military
temperature range per MIL-PRF-38535 QML. Electrical testing ensures compliance of the ’C40 KGD
components to the SMJ320C40 data sheet (literature number SGUS017) over the operating temperature
range. The SMJ320MCM41D module timings are virtually unchanged from the SMJ320C40 data sheet timings.
A SMJ320C40 data sheet is provided for customer reference only and does not imply MCM compliance to
published timings.
For a complete description of the ’C40 operation and application information, refer to the
TMS320C4x User’s
Guide (literature number SPRU063).
capacitance
Capacitance of a single ’C40 die is specified by design to be 15 pF maximum for both inputs and outputs. Module
networks add up to 25 pF. Simulation of die or substrate capacitance is performed after any design change.
Power measurements taken for the ’C40 die are made with an additional 80-pF load capacitance. Refer to the
SMJ320C40 data sheet (literature number SGUS017) for the test load circuit.
operational timings and module testing
TI processing ensures that operation is verified to the published data sheet specifications on the ’C40 in die form.
All voltage, timing, speed, and temperature specifications are met before any die is placed into a multichip
module. For this reason, it is unnecessary to verify all ’C40 voltage and timing parameters at the module level.
Characterization of the ’MCM41D substrate shows that the module performs as an equivalent system of
discretely packaged ’C40 devices. This performance is ensured through a full-frequency functional checkout
of the module that verifies selected worst-case timings. An additional propagation delay is introduced by the
substrate. This value is assured by design to be less than 1 ns, but it is not tested. Refer to the SMJ320C40
data sheet (literature number SGUS017) for a complete listing of timing diagrams and limits.
module test capability (future compatibility)
The ’C40 supports the IEEE-1149.1 testability standard, and all test-access port (TAP) pins are brought out to
the module footprint. This configuration allows users to test the module using third-party JTAG testability tools
or other boundary-scan control software. Proper software configuration allows users to debug or launch code
on the module via the ’C40 emulator and XDS
pod. Both of these tools are used as a part of outgoing module
testing.
The ’MCM41 supports third-party JTAG diagnostic families of products for verification and debug of
boundary-scan circuits, boards, and systems. For further information on JTAG testability tools, please contact
your local TI sales representative or authorized TI distributor.
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