參數(shù)資料
型號: SM320C6701GLPW16
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號處理
英文描述: 32-BIT, 167 MHz, OTHER DSP, CBGA429
封裝: CERAMIC, BGA-429
文件頁數(shù): 44/62頁
文件大小: 873K
代理商: SM320C6701GLPW16
SMJ320C6701
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS030A – APRIL 2000 – REVISED APRIL 2001
49
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP (see Figure 31)
NO.
’C6701-14
’C6701-16
UNIT
NO.
MIN
MAX
UNIT
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
*2P
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
*P – 1
ns
5
t
Set p time e ternal FSR high before CLKR lo
CLKR int
*13
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR ext
4
ns
6
t
Hold time e ternal FSR high after CLKR lo
CLKR int
*7
ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR ext
4
ns
7
t
Set p time DR alid before CLKR lo
CLKR int
10
ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR ext
1
ns
8
t
Hold time DR valid after CLKR low
CLKR int
4
ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR ext
4
ns
10
t
Set p time e ternal FSX high before CLKX lo
CLKX int
*13
ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX ext
4
ns
11
t
Hold time e ternal FSX high after CLKX lo
CLKX int
*7
ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX ext
3
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references
of that signal are also inverted.
*This parameter is not tested.
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