參數(shù)資料
型號(hào)： SLE4432C
廠商： SIEMENS A G
元件分類： DRAM
英文描述： ICs for Chip Cards Intelligent 256-Byte EEPROM
中文描述： 256 X 8 I2C/2-WIRE SERIAL EEPROM, UUC
封裝： DIE
文件頁(yè)數(shù)： 12/35頁(yè)
文件大小： 1011K
代理商： SLE4432C
SLE 4432
SLE 4442
Semiconductor Group
10
2.2.1 Reset and Answer-to-Reset
Answer-to-Reset takes place according to ISO standard 7816-3 (ATR). The reset can be given at
any time during operation. In the beginning, the address counter is set to zero together with a clock
pulse and the first data bit (LSB) is output to I/O when RST is set from level H to level L. Under a
continuous input of additional 31 clock pulses the contents of the first 4 EEPROM addresses is read
out. The 33rd clock pulse switches I/O to high impedance Z and finishes the ATR procedure.
Figure 2
Reset and Answer-to-Reset
2.2.2 Operational Modes
Command Mode
After the Answer-to-Reset the chip waits for a command. Every command begins with a start
condition, includes a 3 bytes long command entry followed by an additional clock pulse and ends
with a stop condition.
– Start condition: Falling edge on I/O during CLK in level H
– Stop condition: Rising edge on I/O during CLK in level H
After the reception of a command there are two possible modes:
– Outgoing data mode for reading
– Processing mode for writing and erasing
Answer-to-Reset
(Hex)
Byte 1
Byte 2
Byte 3
Byte 4
DO
7
… DO
0
DO
15
… DO
8
DO
23
… DO
16
DO
31
… DO
24
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